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lt 8709 1 8709fa for more information www.linear.com/lt8709 typical application features description negative input synchronous multi-topology dc/dc controller 250khz, ?16v to ?30v input to ?12v/8.5a output buck efficiency and power loss vs load current (?v in = ?24v) applications l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. the lt ? 8709 is a synchronous pwm controller for negative - to-negative or negative-to-positive dc/dc conversion, with rail-to-rail output current monitor and control. the lt8709 is ideal for many local power supply designs. it can be easily configured in buck, boost, buck-boost, and inverting topologies with negative input voltages. in addition, the lt8709s rail-to-rail output current sense allows the part to be configured in current limited applica - tions such as battery or capacitor charging . the pg pin is used for power good indication.the lt8709 s switching frequency range can be set between 100khz and 750 khz. the part may be clocked internally at a frequency set by the resistor from the rt pin to the Cv in pin, or it may be synchronized to an external clock. the lt8709 also features innovative en/fbin pin circuitry that allows for slowly varying input signals and an adjust - able undervoltage lockout function. the pin is also used for input voltage regulation to avoid collapsing a high imped- ance input supply. additional features such as frequency foldback, thermal shutdown and soft-start are integrated. the lt8709 is available in a 20-lead tssop package. n wide negative input range: ?4.5v to ?80v n rail-to-rail output current monitor and control n input voltage regulation for high impedance inputs n power good indication pin n mode pin for forced ccm (continuous conduction mode) or pulse-skipping/dcm (discontinuous conduction mode) operation n switching frequency up to 750khz n easily configurable as a buck, boost, buck-boost, or inverting converter with a single feedback pin n can be synchronized to an external clock n high gain en/fbin pin accepts slowly varying input signals n 20- lead tssop package n high power negative input, negative output power supplies n high power negative input, positive output power supplies n telecom equipment power supplies n cathodic protection power supplies load current (a) 0 efficiency (%) power loss (w) 100 80 9060 40 30 7050 20 10 4.53.5 4.02.5 1.5 3.02.0 1.0 0.5 0 5 2 7 8 9 8709 ta01b 3 4 1 6 imon ss Cv in csp bg csn tg lt8709 8709 ta01a intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isn isp v out C12v8.5a Cv in C16v to C30v Cv in 7.3h 4m 120f 2.2f 22f3 10k 2.2f 10f6 143k 100k 2m 62.5k 33k 5.9k 150f + 68nf 470nf 2.2nf 100pf + 2.2f 2.2f 4.99k downloaded from: http:///
lt 8709 2 8709fa for more information www.linear.com/lt8709 pin configuration absolute maximum ratings (note 1) fe package 20-lead plastic tssop 12 3 4 5 6 7 8 9 10 top view 2019 18 17 16 15 14 13 12 11 fby v c ss pg imon isn isp bias intv ee tg Cv in syncrt mode en/fbin csp csn gnd intv cc bg 21 Cv in t jmax = 125c, ja = 38c/w, jc = 10c/w exposed pad (pin 21) is Cv in , must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8709efe#pbf lt8709efe#trpbf lt8709fe 20-lead plastic tssop C40c to 125c lt8709ife#pbf lt8709ife#trpbf lt8709fe 20-lead plastic tssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. gnd voltage with reference to Cv in .......... C0.3 v to 80 v bias voltage with reference to Cv in ......... C0.3 v to 80 v bg voltage with reference to Cv in .................... ( note 5) tg voltage with reference to bias .................... ( note 5) rt voltage with reference to Cv in ............... C0.3 v to 5v ss voltage with reference to Cv in ............... C0.3 v to 3v fby voltage with reference to gnd ............. C3 v to 0.3 v v c voltage with reference to Cv in ............... C0.3 v to 2v en / fbin voltage with reference to Cv in .... C0.3 v to 80 v sync voltage with reference to Cv in ....... C0.3 v to 5.5 v pg voltage with reference to Cv in .............. C0.3 v to 7v pg current ............................................................. 1 ma mode voltage with reference to Cv in ....... C0.3 v to 40 v intv cc voltage with reference to Cv in ....... C0.3 v to 7v intv ee voltage with reference to bias ............. ( note 5) csp voltage with reference to Cv in ............ C0.3 v to 2v csn voltage with reference to Cv in ............ C0.3 v to 2v isp voltage ................................. isn C 0.4 v to isn + 2v isn voltage with reference to Cv in ........... C0.3 v to 80 v imon voltage with reference to Cv in ....... C0.3 v to 2.5 v operating junction temperature range lt 8709 e............................................. C40 c to 125 c lt 8709 i ............................................. C40 c to 125 c storage temperature range .................. C65 c to 150 c ( http:// www .linear.com/product/lt8709#orderinfo ) downloaded from: http:///
lt 8709 3 8709fa for more information www.linear.com/lt8709 electrical characteristics parameter conditions min typ max units minimum operating input voltage v gnd C v Cvin or v bias C v Cvin v gnd C v Cvin , if v bias C v Cvin 4.5v l 0 4.25 4.5 v v quiescent current, i gnd , not switching v bias C v Cvin = 8v, v isn C v Cvin = 8v v bias C v Cvin = 6.3v, v bias C v intvee = 6.3v 4 5.5 5.5 7.5 ma ma quiescent current in shutdown, i gnd v en/fbin = 0v 0 1 a en/fbin minimum input voltage high, releases ss en/fbin rising l 1.64 1.7 1.76 v en/fbin minimum input voltage high, chip-on but ss held low en/fbin rising en/fbin falling l l 1.22 1.18 1.3 1.26 1.38 1.34 v v en/fbin minimum input v oltage high hysteresis 44 mv en/fbin input voltage low shutdown mode l 0.3 v en/fbin pin bias current v en/fbin = 3v v en/fbin = 1.7v v en/fbin = 1.6v v en/fbin = 0v 14 13 44 19.5 17.5 0 60 25 22.5 0.1 a a a a ss charge current v ss = 50mv, current flowing out of ss pin l 7 10.1 13.8 a ss low detection voltage part exiting undervoltage lockout l 18 50 82 mv ss hi detection voltage ss rising ss falling 1.5 1.3 1.8 1.7 2.1 2.05 v v ss hi detection hysteresis 100 mv low dropout regulators, intv cc and intv ee intv cc voltage i intvcc = 10ma l 6.2 6.3 6.4 v intv cc undervoltage lockout intv cc rising intv cc falling l l 3.88 3.5 4 3.73 4.12 3.95 v v intv cc undervoltage lockout hysteresis 270 mv intv cc dropout voltage , v gnd C intv cc v gnd C v Cvin = 6v, v bias C v Cvin = 0v, i intvcc = 10ma v gnd C v Cvin = 0v, v bias C v Cvin = 6v, i intvcc = 10ma 255 280 mv mv intv cc load regulation v gnd C v Cvin = 0v, i intvcc = 0ma to 80ma v bias C v Cvin = 0v, i intvcc = 0ma to 40ma C0.44 C0.34 C2 C2 % % intv cc line regulation 10v v gnd C v Cvin 80v, v bias C v Cvin = 0v, i intvcc = 10ma 10v v bias C v Cvin 80v, v gnd C v Cvin = 0v, i intvcc = 10ma C0.003 C0.006 C0.03 C0.03 %/v %/v intv cc maximum external load current 5 ma intv ee voltage, v bias C v intvee i intvee = 10ma l 6.03 6.18 6.33 v intv ee undervoltage lockout, v bias C v intvee v bias C v intvee rising v bias C v intvee falling l l 3.24 2.94 3.42 3.22 3.6 3.48 v v intv ee undervoltage lockout hysteresis, v bias C v intvee 200 mv intv ee dropout voltage, v intvee C v Cvin v bias C v Cvin = 6v, i intvee = 10ma 0.75 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at t a = 25c. v gnd ? v ?vin = 12v, v en/fbin ? v ?vin = 12v, v bias ? v ?vin = 12v, unless otherwise noted. pin voltages have the following relations: fby is relative to the gnd pin, tg and intv ee to the bias pin, and all other pins to the ? v in pin, unless otherwise stated. pin currents have the following relations: positive current is denoted as current flowing into the pin; negative current is denoted as current flowing out of the pin, unless otherwise stated. (note 2) downloaded from: http:///
lt 8709 4 8709fa for more information www.linear.com/lt8709 parameter conditions min typ max units control loops (refer to block diagram to locate amplifiers) current limit voltage, v csp C v csn i fby = C67.9a, minimum duty cycle i fby = C67.9a, maximum duty cycle l l 46 23 50 31 54 38 mv mv i fby = C108a, mode = 0v, minimum duty cycle i fby = C108a, mode = 0v, maximum duty cycle l l C41 C65 C32 C51 C23 C38 mv mv fby v oltage for negative output voltage regulation q1 conducting current, current flowing out of fby pin l C1.28 C1.234 C1.18 v fby voltage for positive output voltage regulation m1 conducting current, current flowing into fby pin l C60 C15.8 25 mv negative fby pin bias current current flowing out of fby pin l 81.4 83.5 85.7 a positive fby pin bias current current flowing into fby pin l 80.1 83.9 87.5 a fby voltage-to-current amp transconductance, i fby /v fby current flowing out of fby pin, i fby = 10a current flowing into fby pin, i fby = 10a 1.8 1.05 ms ms fby error amp transresistance v vc /i fby current flowing out of fby pin, v vc = 200mv current flowing into fby pin, v vc = 200mv 508 516 k k fby error amp current gain i vc /i fby i vc = 2a 1.5 a/a fby line regulation 4.5v v gnd C v Cvin 80v, v bias C v Cvin = 0v C0.02 0.003 0.02 %/v output current sense regulation voltage, v isp C v isn v isn = 80v, i fby = C53a v isn = 12v, i fby = C53a v isn = 0v, i fby = C53a v isn = 12v, i fby = C53a, intv ee in uvlo and ss > 1.8v l l l l 43 43 40 17 50 50 50 25 57 57 60 34 mv mv mv mv imon regulation v oltage, ea2 i fby = C53a i fby = C53a, intv ee in uvlo and ss > 1.8v l l 1.184 0.885 1.213 0.916 1.24 0.947 v v output current sense amp transconductance, a7 i imon = 10a 1000 s output current sense amp voltage gain, a7 11.9 v/v output current sense amp input dynamic range, a7 negative input range positive input range 500 C51.8 mv mv imon amp t ransconductance, ea2 i vc = 2a, i fby = C53a 165 s imon amp voltage gain, ea2 v isn = 12v, i fby = C53a 65 v/v en/fbin input regulation voltage, ea3 i fby = C53a l 1.55 1.607 1.662 v en/fbin amp transconductance, ea3 i vc = 2a, i fby = C53a 140 s en/fbin amp voltage gain, ea3 i fby = C53a 55 v/v mode forced ccm threshold to exit forced ccm mode, mode rising to enter forced ccm mode, mode falling l l 1.19 1.125 1.224 1.175 1.258 1.23 v v mode for ced ccm threshold hysteresis 49 mv dcm comparator threshold in pulse-skipping mode, mode = 2v v isn = 80v, to enter dcm mode, v isp C v isn falling v isn = 12v, to enter dcm mode, v isp C v isn falling v isn = 0v, to enter dcm mode, v isp C v isn falling l l l C4.5 C4.5 C7.5 2.8 2.8 2.8 10 10 13 mv mv mv dcm comparator threshold in for ced ccm, mode = 0v v isn = 80v, to enter dcm mode, v isp C v isn falling v isn = 12v, to enter dcm mode, v isp C v isn falling v isn = 0v, to enter dcm mode, v isp C v isn falling l l l C380 C380 C380 C300 C300 C300 C220 C220 C220 mv mv mv electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at t a = 25c. v gnd ? v ?vin = 12v, v en/fbin ? v ?vin = 12v, v bias ? v ?vin = 12v, unless otherwise noted. pin voltages have the following relations: fby is relative to the gnd pin, tg and intv ee to the bias pin, and all other pins to the ? v in pin, unless otherwise stated. pin currents have the following relations: positive current is denoted as current flowing into the pin; negative current is denoted as current flowing out of the pin, unless otherwise stated. (note 2) downloaded from: http:///
lt 8709 5 8709fa for more information www.linear.com/lt8709 parameter conditions min typ max units oscillatorswitching frequency, f osc r t = 46.4k r t = 357k l l 640 85 750 100 860 115 khz khz switching frequency in foldback compared to normal f osc 1/5 ratio switching frequency range free-running or synchronizing l 100 750 khz sync high level for sync l 1.5 v sync low level for sync l 0.4 v sync clock pulse duty cycle v sync = 0v to 3v 20 80 % recommended min sync ratio f sync /f osc 3/4 gate drivers, bg and tg bg rise time c bg = 3300pf (note 3) 24 ns bg fall time c bg = 3300pf (note 3) 21 ns tg rise time c tg = 3300pf (note 3) 15 ns tg fall time c tg = 3300pf (note 3) 16 ns bg and tg non-overlap time tg rising to bg rising, c bg = c tg = 3300pf (note 3) bg falling to tg falling, c bg = c tg = 3300pf (note 3) 80 45 140 90 220 150 ns ns bg minimum on-time c bg = c tg = 3300pf 150 420 ns bg minimum off-time c bg = c tg = 3300pf 100 480 ns tg minimum on-time c bg = c tg = 3300pf 0 150 ns tg minimum off-time c bg = c tg = 3300pf 290 770 ns power good indicators, pgpg power good threshold for negative fby voltage current out of fby pin rising current out of fby pin falling l l 71 63.5 74.9 67.5 79 71.5 a a pg power good threshold for positive fby v oltage current into fby pin rising current into fby pin falling l l 71.5 63.5 75.4 67.5 79.5 71.5 a a pg power good hysteresis for negative fby v oltage 7.4 a pg power good hysteresis for positive fby voltage 7.9 a pg anti-glitch delay delay from pg threshold trip to pg toggle 100 s pg output voltage low 100a into pg pin, |i fby | < pg threshold l 9 50 mv pg leakage current v pg = 7v, |i fby | > pg threshold 0.01 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8709e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating temperature range are assured by design, characterization and correlation with statistical process controls. the lt8709i is guaranteed over the full C40c to 125c operating junction temperature range. note 3: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels.note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active . continuous operation over the specified maximum operating junction temperature may impair device reliability. note 5: do not apply a positive or negative voltage or current source to the bg, tg, and intv ee pins, otherwise permanent damage may occur, except intv ee may be connected to Cv in if bias is connected to intv cc . electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at t a = 25c. v gnd ? v ?vin = 12v, v en/fbin ? v ?vin = 12v, v bias ? v ?vin = 12v, unless otherwise noted. pin voltages have the following relations: fby is relative to the gnd pin, tg and intv ee to the bias pin, and all other pins to the ? v in pin, unless otherwise stated. pin currents have the following relations: positive current is denoted as current flowing into the pin; negative current is denoted as current flowing out of the pin, unless otherwise stated. (note 2) downloaded from: http:///
lt 8709 6 8709fa for more information www.linear.com/lt8709 positive and negative feedback voltage vs temperature positive and negative fby currents vs temperature input regulation voltage vs temperature (en/fbin) input regulation voltage vs fby (en/fbin) current sense voltage vs temperature (isp-isn and imon) current sense voltage vs fby (isp-isn and imon) max current limit vs duty cycle (csp - csn) max current limit vs temperature (csp - csn) max current limit vs ss (csp - csn) typical performance characteristics duty cycle (%) 0 max positive csp-csn (mv) max negative csp-csn (mv) 6050 5540 30 4535 25 20 C20C30 C25C40 C50 C35C45 C55 C60 50 20 70 80 90 8709 g01 100 30 40 10 60 f osc = 300khz ss (v) 0.0 csp-csn (mv) 6040 5030 20 10 0 0.8 0.2 1 1.2 1.4 8709 g03 1.6 0.4 0.6 temperature (c) C50 max positive csp-csn (mv) max negative csp-csn (mv) 5652 5450 48 46 44 C26C30 C28C34 C32C36 C38 50 C25 75 100 8709 g02 125 0 25 temperature (c) C50 positive fby voltage (mv) negative fby voltage (v) 10 0 5 C10 C5 C15C20 C25 C30 C1.220C1.230 C1.225C1.240 C1.245 C1.250 C1.235C1.255 C1.260 50 C25 75 100 8709 g04 125 0 25 temperature (c) C50 positive fby current into pin (a) negative fby current out of pin (a) 86.085.0 85.584.0 83.5 83.0 84.582.5 82.0 81.5 86.085.0 85.584.0 83.5 83.0 84.582.5 82.0 81.5 50 C25 75 100 8709 g05 125 0 25 temperature (c) C50 en/fbin voltage (v) 1.631.61 1.621.60 1.59 1.58 1.57 C25 50 75 100 8709 g06 125 0 25 fby current (a) 10 en/fbin (v) 2.01.8 1.91.7 1.6 1.5 1.4 20 50 60 70 80 8709 g07 90 30 40 temperature (c) C50 average isp-isn (mv) imon (v) 57.552.5 55.050.0 47.5 45.0 42.5 1.21751.2125 1.21501.2100 1.2075 1.2050 1.2025 C25 50 75 100 8709 g08 125 0 25 imon ave isp-isn fby current (a) 10 average isp-isn (mv) imon (v) 6050 5545 40 35 30 1.301.20 1.251.15 1.10 1.05 1.00 20 50 60 70 80 8709 g09 90 30 40 imon ave isp-isn t a = 25c, all voltages relative to ?v in unless otherwise noted. downloaded from: http:///
lt 8709 7 8709fa for more information www.linear.com/lt8709 mode pin threshold vs temperature (rising and falling) en/fbin thresholds vs temperature (1.7v and 1.3v) en/fbin pin current (0v to 2v) vs temperature en/fbin pin current (0v to 80v) vs temperature oscillator frequency vs temperature (100khz and 750khz) oscillator frequency during soft-start bg and tg transition time vs cap load dcm comparator threshold vs temperature pg threshold vs temperature (rising and falling) typical performance characteristics cap load (nf) 0 transition time (ns) 8070 60 40 30 10 50 20 0 2 8 10 8709 g18 4 6 bg rising bg falling tg rising tg falling t a = 25c, all voltages relative to ?v in unless otherwise noted. temperature (c) C50 isp-isn (mv) isp-isn (mv) 64 53 2 1 0 C280C300 C290C310 C320 C330 C340 C25 50 75 100 8709 g10 125 0 25 mode = 0v, fcm mode = 2v, dcm temperature (c) C50 mode (v) 1.241.22 1.231.21 1.20 1.18 1.17 1.19 1.16 1.15 1.14 C25 50 75 100 8709 g12 125 0 25 falling rising en/fbin voltage (v) 0 en/fbin pin current (a) 3530 25 15 10 20 5 0 0.25 1 1.25 1.5 1.75 8709 g14 2 0.5 0.75 C40c25c 125c en/fbin voltage (v) 0 en/fbin pin current (a) 600500 400 200 300 100 0 10 40 50 60 70 8709 g15 80 20 30 C40c25c 125c temperature (c) C50 f osc (khz) 900800 700 500 400 200 100 600 300 0 C25 50 75 100 125 8709 g16 0 25 r t = 46.4k r t = 357k temperature (c) C50 en/fbin chip enable (v) en/fbin active mode (v) 1.401.36 1.381.34 1.32 1.28 1.26 1.30 1.24 1.22 1.20 1.751.71 1.731.69 1.67 1.63 1.61 1.59 1.57 1.651.55 C25 50 75 100 8709 g13 125 0 25 falling rising rising only fby current (a) C75 normalized oscillator frequency (f sw /f nom ) 1 1/21/3 1/5 1/4 0 C50 25 50 75 8709 g17 C25 0 inverting configurations noninverting configurations temperature (c) C50 positive fby current pin (a) negative fby current out of pin (a) 8078 75 73 70 68 65 8078 75 73 70 68 65 C25 50 75 100 8709 g11 125 0 25 negative rising negative falling positive falling positive rising downloaded from: http:///
lt 8709 8 8709fa for more information www.linear.com/lt8709 intv cc current limit vs gnd or bias intv cc dropout from gnd or bias intv ee vs temperature intv ee uvlo vs temperature (rising and falling) intv ee current limit vs bias intv ee dropout (bias = 6v) minimum operating input voltage intv cc vs temperature intv cc uvlo vs temperature (rising and falling) typical performance characteristics intv ee load current (ma) 10 0 intv ee Cv Cvin (v) 1.21.0 0.9 0.8 0.6 0.5 0.7 1.10.4 50 8709 g27 20 30 40 C40c25c 125c temperature (c) C50 gnd or v bias (v) 4.354.33 4.29 4.25 4.23 4.21 4.19 4.17 4.31 4.27 4.15 C25 75 100 125 8709 g19 0 25 50 temperature (c) C50 intv cc (v) 6.406.28 6.24 6.36 6.32 6.20 C25 75 100 125 8709 g20 0 25 50 i intvcc = 10ma temperature (c) C50 intv cc (v) 4.23.9 3.8 3.7 3.6 4.1 4.0 3.5 C25 75 100 125 8709 g21 0 25 50 rising falling input voltage (v) 10 intv cc current limit (ma) 150100 7550 25 125 0 20 60 70 80 8709 g22 30 40 50 gnd bias gnd or bias intv cc > 3.5v intv cc > 3.5v intv cc < 3.5v intv cc load current (ma) 10 0 input - intv cc (v) 500400 350 300 250 450200 20 60 70 80 8709 g23 30 40 50 gnd bias temperature (c) C25 C50 bias - intv ee (v) 6.286.20 6.16 6.12 6.246.08 0 100 125 8709 g24 25 50 75 i intvee = 10ma temperature (c) C25 C50 bias - intv ee (v) 3.63.4 3.3 3.2 3.1 3.53.0 0 100 125 8709 g25 25 50 75 falling rising bias (v) 20 10 intv ee current limit (ma) 7545 6030 15 0 30 70 80 8709 g26 40 50 60 bias - intv ee =5v t a = 25c, all voltages relative to ?v in unless otherwise noted. downloaded from: http:///
lt 8709 9 8709fa for more information www.linear.com/lt8709 pin functions fby ( pin 1): feedback pin. its voltage is referred to the gnd pin. for a boost, buck-boost, or inverting converter, tie a resistor from the fby pin to v out according to the following equations: r fby = | v out | C1.234v 83.5a negative output voltage r fby = v out + 15.8mv 83.9a positive output voltage see the applications section for more information.v c ( pin 2): error amplifier output pin. its voltage is re- ferred to the C v in pin. connect an external compensation network between this pin and the Cv in pin. ss ( pin 3): soft-start pin. its voltage is referred to the C v in pin. place a soft - start capacitor here that is about 5 greater than the imon capacitor. upon start-up, the ss pin will be charged by a nominal 260 k resistor to ~2.7 v. during a current overload as seen by isp-isn, overtemperature, or uvlo condition, the ss pin will be quickly discharged to reset the part. once these conditions have cleared, the part will attempt to restart. pg ( pin 4): power good indication pin. its voltage is referred to the C v in pin. the pg pin functions as an ac- tive high power good pin. power is good when the fby pin current is C74.9 a or 75.4 a (~90% of the regulation current), which corresponds to ~90% of the regulation voltage on v out . for power good indication, there is a 100s anti-glitch delay. a pull-up resistor or some other form of pull -up network is required on this pin to use the feature. see the block diagram and applications section for more information.imon ( pin 5): output current sense monitor pin. its voltage is referred to the C v in pin. outputs a voltage that is proportional to the voltage between the isp and isn pins, as given below. v imon = 11.9 ? (v isp C isn + 51.8mv) since the voltage across the isp and isn pins is ac, a filtering capacitor is needed between the imon and C v in pins to average out the isp and isn voltage. recommended capacitor values are from 10 nf C 100 nf. a 51.8 mv offset is added to the amplifier such that an average voltage of 0v on isp-isn corresponds to a imon voltage of 616 mv. when the average voltage across the isp and isn pins is 50mv, the imon pin will output ~1.213 v . do not resistively load down this pin. isn, isp ( pins 6, 7): output current sense negative and positive input pins respectively. kelvin connect the isn and isp pins to a sense resistor to limit the output cur - rent. the commanded nfet current will limit the voltage difference across the sense resistor to 50mv.bias ( pin 8): additional input supply and tg gate driver high voltage rail. bias is a second positive input sup- ply pin in addition to gnd and must be locally bypassed to C v in . the bias pin sets the top rail for the tg gate driver. bias must be connected to the converters v out for a negative inverting converter, or intv cc for a negative boost converter, or gnd for a negative buck or negative buck-boost converter. intv ee ( pin 9): 6.18v-below-bias regulator pin. must be locally bypassed to bias with a minimum capacitance of 2.2f. this pin sets the bottom rail for the tg gate driver. the tg gate driver can begin switching when bias C intv ee exceeds 3.42 v ( typical). connect this pin to C v in for a negative boost converter.tg ( pin 10): pfet gate drive pin. low and high levels are bias C intv ee and bias respectively. bg ( pin 11): nfet gate drive pin. low and high levels are Cv in and intv cc respectively. intv cc ( pin 12): 6.3 v dual input ldo regulator pin. its voltage is referred to the C v in pin. must be locally bypassed to C v in with a minimum capacitance of 2.2 f. logic will choose to run intv cc from the gnd or bias pins. a maximum 5 ma external load can connect to the intv cc pin. the bg gate driver can begin switching when intv cc exceeds the 4v (typical) intv cc undervoltage lockout. gnd ( pin 13): positive input supply pin. must be locally bypassed to C v in . can run down to v Cvin as long as bias Cv Cvin > 4.5v. downloaded from: http:///
lt 8709 10 8709fa for more information www.linear.com/lt8709 pin functions csn, csp ( pins 14, 15): nfet current sense negative and positive input pins respectively. kelvin connect these pins to a sense resistor to control the nfet switch current. the maximum sense voltage at low duty cycle is 50mv (typical).en/fbin ( pin 16): enable and input voltage regulation pin. its voltage is referred to the C v in pin. in conjunction with the intv cc and intv ee uvlo ( undervoltage lockout) circuits, overtemperature protection and output overcur- rent protection ; this pin is used to enable/disable the chip and restart the soft-start sequence. the en/fbin pin is also used to limit the nfet current to avoid collapsing the input supply. drive the pin below 0.3 v to disable the chip with very low quiescent current. drive the pin above 1.7v ( typical) to activate the chip and restart the soft-start sequence. the commanded nfet current will be controlled by the en/fbin amplifier when the voltage drops between 1.55v and 1.662 v. see the block diagram and applica - tions section for more information. do not float this pin. mode ( pin 17): dcm / ccm mode pin. its voltage is referred to the C v in pin. drive the pin below 1.175 v ( typical) to operate in forced ccm. drive the pin above 1.224 v ( typi- cal) to operate in dcm and/or pulse-skipping mode at light loads. if ss < 1.8 v ( typical) or intv ee is in uvlo, the part will operate in dcm at light load.rt ( pin 18): timing resistor pin. adjusts the lt8709s switching frequency. place a resistor from this pin to C v in to set the frequency to a fixed free running level. do not float this pin.sync ( pin 19): external clock input pin. its voltage is referred to the C v in pin. to synchronize the switching frequency to an outside clock, simply drive this pin with a clock to override the internal clock. the logic-high voltage level of the sync clock must exceed 1.5 v, and the logic- low level must be less than 0.4 v. drive this pin to less than 0.4 v to revert to the internal free running clock. see the applications information section for more information . ?v in ( pin 20, exposed pad pin 21): negative voltage input pin. since C v in also serves as the chip ground, it must be soldered onto a local Cv in plane on the pcb. downloaded from: http:///
lt 8709 11 8709fa for more information www.linear.com/lt8709 block diagram figure 1. block diagram 2.7v mode dcm_en isn 1.155v fbx pg isp 1:1 dcm_en 8709 bd tg driver disable ? + ss Cv in Cv in Cv in Cv in Cv in Cv in Cv in uvlo 100s anti-glitch level shift start-up and reset logic adjustable oscillator soft-start 51.4k 1.3v 1.7v r in2 ? + ea1 rt logic-lo ?v in + 0.4v logic-hi ?v in + 1.5v v c r c r t sync imon isn fby isp n ss en/fbin 1.607v sync block slope compensation c vcc 6.3v ?v in ?v in ?v in ?v in ?v in ?v in ?v in ?v in ?v in note: all the voltages inside the chip are referred to the ?v in pin. gnd intv cc en/fbin bias csn mp mn r sense1 r sense2 bg tg tg tg bias driver driver bias ? 6.18v intv ee pg intv cc bias ? + a5 csp c in ldo logic ldo uvlo 1.213v reference en/fbin logic imon1.38v ? + die temp175c ? + 1.234v q1m1 fbx 1.213v ? + 1.224v ? + 1.8v ? + 50mv fbx dcm_en 260k driverdisable c ss r in1 frequency foldback a6 sr1 r s q ? + ? + ? + 14.5k14.5k 1.213v 11.9k 51.8mv r fby ? + ea3 ? + ea2 ? + a7 +? c imon c f c c ldo c vee l1 + ? c out v out downloaded from: http:///
lt 8709 12 8709fa for more information www.linear.com/lt8709 state diagram figure 2. state diagram 8709 sd ? all switches disabled chip off ? ss pulled low? intv cc charges up initialize ? ss slowly charges up? v c pulled low active mode ? pfet turns off for remainder of cycle if isp-isn voltage falls below 2.8mv (typ) ? for very light load, part may skip pulses dcm at light load ? v c commands peak inductor current to maintain regulation regulation ? output current limited to 25mv average across the isp-isn pins output current foldback ? bg and tg switch at constant frequency ? inductor current can reverse ? if isp-isn voltage goes below C300mv (typ), pfet turns off so inductor current goes more positive forced ccm operation ? ss discharges quickly ? switcher disabled en/fbin < 1.3v (typ) or gnd and bias < 4.5v (max) 1.3v < en/fbin < 1.7v (typ) and gnd or bias > 4.5v en/fbin > 1.7v and gnd or bias > 4.5v and intv cc > 4v (typ) intv ee regulator in uvlo and ss > 1.8v (typ) mode < 1.175v (typ) and ss > 1.8v (typ) mode > 1.224v (typ) ss < 50mv reset reset detected ? no reset conditions detected reset over reset reset ? nfet begins switching? pfet starts switching when intv ee regulator is not in uvlo begin switching reset reset reset regulation = output voltage (fby)input voltage (en/fbin) output current (isp-isn and imon) reset = uvlo on gnd or bias ( < 4.5v (max))uvlo on intv cc ( < 4v (typ)) en/fbin < 1.7v (typ) at 1st power-upen/fbin < 1.26v (typ) after active mode set overcurrent (isp C isn > 63.6mv average (typ)) overtemperature (t j > 175c (typ)) note: all voltages are referred to the Cv in pin voltage. downloaded from: http:///
lt 8709 13 8709fa for more information www.linear.com/lt8709 operation operation ? overview throughout the whole context of this data sheet, keep in mind the following voltage relations : 1) fby is relative to the gnd pin; fby positive or negative current refers to current flowing into or out of the fby pin 2) tg and intv ee are relative to the bias pin; and 3) all other pins, including the bias pin, are relative to the ?v in pin. the lt8709 uses a constant frequency, current mode control to provide excellent line and load regulation. the parts undervoltage lockout ( uvlo) function, together with soft-start and frequency foldback, offers a controlled means of start - up. output voltage, output current, and input voltage have control over the commanded peak current, which allows for a wide range of applications to be built using the lt8709. synchronous switching makes high efficiency and high output current applications possible. when operating at light currents with the mode pin > 1.224v ( typical), the lt8709 will disable synchronous operation for part of the cycle to prevent negative switch currents. refer to the block diagram ( figure 1) and the state diagram ( figure 2) for the following description of the parts operation. operation ? start-up several functions are provided to enable a very clean start-up of the lt8709.precise t urn-on voltages the en/fbin pin has two voltage levels for activating the part: the 1 st one enables the part and allows internal rails to operate; and the 2 nd voltage threshold activates a soft- start cycle and thus allows switching to begin. to enable the part, take the en/fbin pin above 1.3 v ( typical). this comparator has 44 mv of hysteresis to protect against glitches and slow ramping. to activate a soft-start cycle and allow switching, take the en/fbin above 1.7 v ( typi - cal). when en/fbin exceeds 1.7 v ( typical), the logic state is latched so that if en/fbin drops between 1.3 v to 1.7 v (typical), the ss pin is not pulled low by the en/fbin pin. the en/fbin pin is also used for input voltage regulation which is at 1.607 v ( typical). input voltage regulation is explained in more detail in the operation C regulation section. taking the en/fbin pin below 0.3 v shuts down the chip, resulting in extremely low quiescent current. see figure 3 for the different en/fbin voltage thresholds. undervoltage lockout (uvlo) the lt8709 has internal uvlo circuitry that disables the chip when the greater of gnd or bias < 4.5 v ( maximum) or intv cc < 4 v ( typical). the en/fbin pin can also be used to create a configurable uvlo. see the applications section for more information.soft-start of switch current the soft-start circuitry provides for a gradual rise of the switch current ( refer to max current limit vs ss(csp? csn ) in typical performance characteristics). when the part is brought out of shutdown, the external ss capacitor is first discharged, which resets the states of the logic circuits in the chip. once intv cc is out of uvlo (> 4 v typical) and the chip is in active mode, an integrated 260k resistor pulls the ss pin to ~2.7 v at a ramp rate set by the external capacitor connected to the pin. typical values for the soft - start capacitor range from 100 nf to 1 f. the soft-start capacitor should also be about 5 greater than the external capacitor connected to the imon pin to avoid start-up issues. figure 3. en/fbin modes of operation 8709 f03 active mode threshold (tolerance) normal operation if active mode set input voltage regulation (only if active mode set) en/fbin (v) with reference to the Cv in pin chip enable threshold (hystersis and tolerance) lockout (switch off, ss cap discharged, intv cc and intv ee disabled) shutdown (low quiescent current) switch off, intv cc and intv ee enabled, ss cap discharged if active mode not set active mode (normal operation) (mode latched until en/fbin drops below chip enable treshold) 1.76v1.64v 1.662v 1.55v1.38v 1.18v 0.3v 0v downloaded from: http:///
lt 8709 14 8709fa for more information www.linear.com/lt8709 frequency foldback the frequency foldback circuitry reduces the switching frequency when the fby pin current < 56.9 a ( typical). this feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current at start-up. when the fby current exceeds this value, the switching frequency returns to normal. if the part is configured to be in forced continuous conduction mode (mode pin is driven below 1.175 v), then the frequency foldback circuitry is disabled as long as intv ee is not in uvlo and the ss pin is higher than the ss hi threshold. note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance , target v out , v in , switching frequency, etc. operation ? regulation use the block diagram when stepping through the following description of the lt8709 operating in regulation. also, assume the converters load current is high enough such that the part is operating in synchronous switching. the lt8709 has three modes of regulation: 1. output voltage (via fby pin) 2. input voltage (via en/fbin pin) 3. output current (via isp, isn, and imon pins) all three of these regulation loops control the peak com - manded current through the external nfet, mn. this operation is the same regardless of the regulation mode, so that will be described first. at the start of each oscillator cycle, the sr latch ( sr1) is set, which first turns off the external pfet, mp, and then turns on the external nfet, mn. the nfets source current flows through an external current sense resistor (r sense1 ) generating a voltage proportional to the nfet switch current. this voltage is then amplified by a5 and added to a stabilizing ramp. the resulting sum is fed into the positive terminal of the pwm comparator a6. when the voltage on the positive input of a6 exceeds the voltage on the negative input (v c pin), the sr latch is reset, turning off the nfet and then turning on the pfet. the voltage on the v c pin is controlled by one of the regulation loops, or a combination of regulation loops. for simplicity, each mode of regulation will be described independently so that only one of the regulation loops is in command of the lt8709. output voltage regulation in most cases, a single external resistor is used to set the target output voltage. see the pin functions section for selecting the feedback resistor for a desired output voltage . the v c pin voltage ( negative input of a6) is set by ea1, which is an amplified difference between the fbx voltage , (the product of the fby current and 7.25 k plus 0.6065 v) and the reference voltage (1.213 v). in this manner, the fby error amplifier sets the correct peak current level to maintain output voltage regulation. input voltage regulation there are two ways to set the input voltage regulation: a resistor divider to en/fbin between gnd and C v in or, a single resistor between gnd and en / fbin pins. it is recom - mended to use a resistor divider for improved accuracy as described in the setting the input voltage regulation or undervoltage lockout section. the en/fbin pin volt - age connects to the positive input of amplifier ea3. the v c pin voltage is set by ea3, which is simply an amplified difference between the en/fbin pin voltage and a 1.607 v reference voltage. in this manner, the en / fbin error ampli - fier sets the correct peak current level to maintain input voltage regulation.output current regulation an external sense resistor connected between the isp and isn pins ( r sense2 ) sets the maximum output current of the converter and is placed in series either with the source of the pfet, mp, or in series with the converter output, depending on the type of converter. a built - in 51.8 mv offset is added to the voltage seen across r sense2 . the sensed voltage along with the 51.8 mv offset is then amplified and output to the imon pin. an external capacitor must be placed from imon to C v in to filter the amplified chopped voltage thats sensed across r sense2 . the voltage at the imon pin is fed to the negative input of the imon error amplifier, ea2. the v c pin voltage is set by ea2, which is simply an amplified difference between the imon pin voltage and the 1.213 v reference voltage. in this manner, operation downloaded from: http:///
lt 8709 15 8709fa for more information www.linear.com/lt8709 the imon error amplifier sets the correct peak current level to maintain output current regulation. note that if the intv ee ldo is in uvlo and ss > 1.8 v (typical), then the voltage reference at the positive input of ea2 is 916 mv ( typical), resulting in limiting the output current to about half of the desired limit. operation ? reset conditions the lt8709 has three reset cases. when the part is in reset, the ss pin is pulled low and both power switches, mn and mp, are forced off. once all of the reset conditions are gone, the part is allowed to begin a soft-start sequence and switching can commence. each of the following events can cause the lt8709 to be in reset: 1. uvlo a. the greater of gnd and bias is < 4.5 v ( maximum) b. intv cc < 4v (typical) c. en/fbin < 1.7v (typical) at the first power-up 2. overcurrent sensed by imon > 1.38v (typical) 3. die temperature > 175c operation ? power switch control the primary power switch is the external nfet ( mn in block diagram) and the synchronous secondary power switch is the external pfet ( mp in block diagram). the two switches are never on at the same time, and there is a non-overlap time of ~140 ns and ~90 ns from mp off to mn on and from mn off to mp on, respectively ( see electrical characteristics) to prevent cross conduction. figure 4 below shows the relative timing of the bg and tg (biasCtg) signals: light load current (mode pin) the mode pin can be used to tell the lt8709 to operate in forced ccm regardless of load current, or operate in dcm at light loads. ? mode < 1.175v (typical) = forced ccm or fcm ? mode > 1.224v (typical) = dcm the forced continuous mode ( fcm) allows the inductor current to reverse directions without any switches being forced off. at very light load currents, the inductor cur - rent will swing positive and negative as the appropriate average current is delivered to the output. there are some exceptions that negate the mode pin and force the part to operate in dcm at light loads: 1. the intv ee ldo is in uvlo ( bias C intv ee < 3.42 v typical). 2. ss < 1.8v (typical). 3. the part is in a reset condition. when the lt8709 is in discontinuous mode ( dcm), syn - chronous switch mp is held off whenever mps current falls near 0 current ( less than 2.8 mv ( typical) across r sense2 ). this is to prevent current draw from the output and/or feeding current to the input supply. under very light loads, the current comparator a6, may also remain tripped for several cycles ( i.e. skipping pulses). since mp is held off during the skipped pulses, the inductor current will not reverse. operation ? power good (pg pin) the pg pin is an open-drain pin that functions as an active high power good pin. the pg pin has 100 s ( typical) delay in order to reject glitches or transient events. power is good when fby pin current is C74.9 a or 75.4 a (~90% of the regulation current), which corresponds to ~90% of the regulation voltage on v out . the pg compara- tors have 7.65a of hysteresis to reject glitches. operation figure 4. synchronous switching 8709 f04 bg on tg on 140ns 90ns downloaded from: http:///
lt 8709 16 8709fa for more information www.linear.com/lt8709 operation ? ldo regulators (intv cc and intv ee ) the intv cc ldo regulates to 6.3 v ( typical) and is used as the top rail for the bg gate driver. the intv cc ldo can run from gnd or bias and will minimize power losses by intelligently selecting the lower voltage as long as both are at a high enough voltage above C v in . the intv cc regulator also has safety features to limit the power dissipation in the internal pass device and also to prevent it from dam - age if the pin is shorted to ground. the uvlo threshold on intv cc is 4 v ( typical), and the lt8709 will be in reset until the ldo comes out of uvlo. the intv ee regulator regulates to 6.18 v ( typical) below the bias pin voltage. the bias and intv ee voltages are used for the top and bottom rails of the tg gate driver respectively. just like the intv cc regulator, the intv ee regulator has a safety feature to limit the power dissipation in the internal pass device. the tg pin can begin switch - ing after the intv ee regulator comes out of uvlo (3.42 v typical across the bias and intv ee pins) and the part is not in a reset condition. operation downloaded from: http:///
lt 8709 17 8709fa for more information www.linear.com/lt8709 negative buck converter component selection applications information figure 5. negative buck converter ? the component values given are typical for a 250khz, ?16v to ?30v input to ?12v/8.5a output buck. the lt8709 can be configured as a negative to less negative buck converter as in figure 5. this topology generates a negative output voltage from a more negative input volt - age. resistors r fby1 and r fby2 set the output voltage by regulating fby to C1.234v, referred to gnd. for a desired output load current at the negative output voltage over a given negative input voltage range, table 1 is a step-by-step set of equations to calculate component values for the lt8709 when operating as a negative buck converter. refer to this section and the appendix for further information on the design equations presented in table 1. variable definitions: v in(min) = minimum input voltage v in(max) = maximum input voltage v out = output voltage i out = output load current of converter f = switching frequency dc min = power switch duty cycle at v in(max) dc max = power switch duty cycle at v in(min) v cspn = current limit voltage at dc max table 1. negative buck design equations parameters/equations step 1: inputs pick v in , v out , i out , and f to calculate equations below. step 2: dc max dc min d c max ? v out v in (min) ; dc min ? v out v in (max) step 3: v cspn see max current limit vs duty cycle plot in typical performance characteristics to find v cspn at dc max . step 4: r sense1 r sense1 = 0.58 ? v cspn i out step 5: r sense2 r sense2 = 0.05 1.6 ? i out step 6: l l typ = r sense1 ?(| v in(min) | C | v out |)?dc max 12.5mv ? f (1) l min r sense1 ?| v in(min) | f ? 40mv ?dc max ? 2dc max C 1 ( ) (2) l max r sense1 ?(| v in(min) | C | v out |)?dc max 3mv ? f (3) ? solve equations 1 to 3 for a range of l values.? the minimum value of the l range is the higher of l typ and l min . the maximum of the l value range is l max . step 7: c out c out 1Cdc min 8 ?l ? f 2 ? 0.005 step 8: c in c in i out ? dc max ?(1Cdc max ) f ? 0.005?| v in(min) | step 9: c imon c imon 100a ?dc max 0.005? f step 10: r fby1 , r fby2 r fby2 = 4.99k? ; r fby1 = | v out | C1.234v 83.5a + 1.234v r fby2 step 11: r t r t = 35,880 f C 1; f in khz and r t in k? note: the final values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. the c out and c in equations assume zero esr, so increase the capacitance accordingly based on the effective esr. imon ss Cv in csp bg csn tg lt8709 8709 f05 intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isn isp v out C12v8.5a Cv in C16v to C30v Cv in l1 7.3h mp mn c in1 120f 2.2f c out1 22f3 r in2 10k 2.2f c in2 10f6 r t 143k 100k 2m r in1 62.5k r sense1 r sense2 4m r fby1 33k r fby2 4.99k r c 5.9k c out2 150f + 68nf 470nf c c 2.2nf c f 100pf + 2.2f 2.2f downloaded from: http:///
lt 8709 18 8709fa for more information www.linear.com/lt8709 imon ss Cv in csp tg csn bg lt8709 8709 f06 intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isp isn v out 5v4a Cv in C4.5v to C42v Cv in l1 4.7h mp mn c in1 330f 2.2f c out1 100f4 r in2 10k 2.2f c in2 10f6 r t 178k 100k 1.5m r in1 4.99k r sense1 r sense2 8m r fby 60.4k r c 16.9k c out2 330f + 68nf 470nf c c 3.3nf c f 100pf + 2.2f 2.2f negative inverting converter component selection applications information figure 6. negative inverting converter ? the component values given are typical for a 200khz, ?4.5v to ?42v input to 5v/4a output. the lt8709 can be configured as a negative to positive inverting converter as in figure 6. this topology generates a positive output voltage from a negative input voltage with larger, equal or smaller magnitude. a single feedback resistor sets the output voltage by regulating fby to C15.8mv with reference to the gnd pin voltage. for a desired output load current at the positive output voltage over a given negative input voltage range, table 2 is a step-by-step set of equations to calculate component values for lt8709 when operating as a negative inverting converter . refer to this section and the appendix for further information on the design equations presented in table 2. variable definitions: v in(min) = minimum input voltage v in(max) = maximum input voltage v out = output voltage i out = output load current of converter f = switching frequency dc min = power switch duty cycle at v in(max) dc max = power switch duty cycle at v in(min) v cspn = current limit voltage at dc max table 2. negative inverting converter design equations parameters/equations step 1: inputs pick v in , v out , i out , and f to calculate equations below. step 2: dc max dc min d c max ? v out v out + | v in (min) | ; dc min ? v out v out + | v in (max) | step 3: v cspn see max current limit vs duty cycle plot in typical performance characteristics to find v cspn at dc max . step 4: r sense1 r sense1 = 0.58 ? v cspn i out ?(1Cdc max ) step 5: r sense2 r sense2 = 0.05 1.6 ?i out step 6: l l typ = r sense1 ?| v in(min) | ?dc max 12.5mv ? f (1) l min r sense1 ?| v in(min ) | f ? 40mv ?dc max ? 2dc max C 1 1Cdc max ?? ? ?? ? (2) l max r sense1 ?| v in(min) | ? dc max 3mv ? f (3) ? solve equations 1 to 3 for a range of l values.? the minimum value of the l range is the higher of l typ and l min . the maximum of the l value range is l max . step 7: c out c out i out ?dc max f ? 0.005 ? v out step 8: c in c in i out ?dc max f ? 0.005 ? v in(min) step 9: c imon c imon 100a ?dc max 0.005? f step 10: r fby r fby = | v out |+15.8mv 83.9a step 11: r t r t = 35,880 f C 1; f in khz and r t in k? note: the final values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. the c out and c in equations assume zero esr, so increase the capacitance accordingly based on the effective esr. downloaded from: http:///
lt 8709 19 8709fa for more information www.linear.com/lt8709 imon ss Cv in csp tg csn bg lt8709 8709 f07 intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isp isn v out C5v7a Cv in C4.5v to C25v Cv in l1 3.5h mp 2 mn c in1 330f 2.2f c out1 100f3 r in2 10k 2.2f c in2 10f4 r t 143k 100k 1.5m r in1 13.3k r sense1 r sense2 5m ? l2 3.5h ? r fby 45.3k r c 11k c out2 330f + 68nf 470nf c c 3.3nf c f 100pf + 2.2f c1 10f 2 2.2f negative buck-boost converter component selection ? coupled or uncoupled inductors applications information figure 7. negative buck-boost converter ? the component values given are typical for a 250khz, ?4.5v to ?25v input to ?5v/7a buck-boost topology using coupled inductors. the lt8709 can be configured as a negative buck-boost as in figure 7. this topology generates a negative output voltage from a more, equal or less negative input voltage with very low output voltage ripple due to inductor l2 in series with the output. output disconnect is built into the topology through c1, meaning no dc path exists between the input and output. gnd-referred fby is regulated to C1.234v through a single resistor between v out and fby. for a desired output load current at the negative output voltage over a given negative input voltage range, table 3 is a step-by-step set of equations to calculate component values for lt8709 when operating as a negative buck- boost converter. refer to more detail in this section and the appendix for the design equations. variable definitions: v in(min) = minimum input voltage v out = output voltage i out = output load current of converter f = switching frequency v in(max) = maximum input voltage dc min = power switch duty cycle at v in(max) dc max = power switch duty cycle at v in(min) v cspn = current limit voltage at dc max table 3. negative buck-boost design equations parameters/equations step 1: inputs pick v in , v out , i out , and f to calculate equations below. step 2: dc max dc min dc max ? v out v out + v in (min) ; dc min ? v out v out + v in (max) step 3: v cspn see current limit vs duty cycle plot in typical performance characteristics to find v cspn at dc max . step 4: r sense1 r sense1 = 0.58 ? v cspn i out ?(1Cdc max ) step 5: r sense2 r sense2 = 0.05 1.6 ?i out step 6: l l typ = r sense1 ?| v in(min) | ? dc max 12.5mv ? f (1) l min r sense1 ? |v in(min) | f ? 40mv ?dc max ? 2dc max C 1 1Cdc max ?? ? ?? ? (2) l max r sense1 ? |v in(min) | ? dc max 3mv ? f (3) ? solve equations 1 to 3 for a range of l values.? the minimum value of the l range is the higher of l typ and l min . the maximum of the l value range is l max . ? l = l 1 = l 2 for coupled inductors. ? l = l 1 || l 2 for uncoupled inductors. step 7: c1 c 1 10f typical;v rating > |v out | ( ) step 8: c out c out 1C dc min 8 ?l ? f 2 ? 0.005 step 9: c in c in i out ?dc max f ? 0.005?| v in(min) | step 10: c imon c imon 100a ?dc max 0.005? f step 11: r fby r f by = | v out | C1.234v 83.5a step 12: r t r t = 35,880 f C 1; f in khz and r t in k? note: the final values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. the c out and c in equations assume zero esr, so increase the capacitance accordingly based on the effective esr. downloaded from: http:///
lt 8709 20 8709fa for more information www.linear.com/lt8709 applications information negative boost component selection ? coupled or uncoupled inductors table 4. negative boost design equations parameters/equations step 1: inputs pick v in , v out , i out , and f to calculate equations below. step 2: dc max ; dc min d c max ? 1C v in (min) v out ; dc min ? 1C v in (max) v out step 3: v cspn see current limit vs duty cycle plot in typical performance characteristics to find v cspn at dc max . step 4: r sense1 r sense1 = 0.58 ? v cspn i out ?(1Cdc max ) step 5: r sense2 r sense2 = 0.05 1.6 ?i out step 6: l l typ = r sense1 ?| v in (min) | ? dc max 12.5mv ? f (1) l min r sense1 ? |v in(min) | ? (2dc max C1)/(1Cdc max ) f ? 40mv ? dc max (2) l max r sense1 ? |v in(min) | ? dc max 3mv ? f (3) ? solve equations 1 to 3 for a range of l values.? the minimum value of the l range is the higher of l typ and l min . the maximum of the l value range is l max . ? l = l 1 = l 2 for coupled inductors. ? l = l 1 || l 2 for uncoupled inductors. step 7: c1 c 1 10f typical;v rating > |v out | ( ) step 8: c out c out 1C dc min 8 ?l ? f 2 ? 0.005 step 9: c in c in dc max 8 ?l ? f 2 ? 0.005 step 10: c imon c imon 100a ?dc max 0.005? f step 11: r fby r f by = | v out | C1.234v 83.5a step 12: r t r t = 35,880 f C 1; f in khz and r t in k? note: the final values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. the c out and c in equations assume zero esr, so increase the capacitance accordingly based on the combined esr. figure 8. negative boost converter ? the component values given are typical for a 300khz, ?4.5v to ?9v input to ?12v/4.5a output boost topology using coupled inductors. the lt8709 can work in a negative boost configuration as in figure 8. changing the connection from gnd to C v in for the source of the pfet in the negative buck-boost topology ( figure 7) results in generating a more negative output voltage. this solution gives rise to very low output voltage ripple due to inductor l2 in series with the output. fby is regulated to C1.234 v with reference to the gnd pin voltage. for a desired output current and output voltage over a given input voltage range, table 4 is a step-by-step set of equations to calculate component values for the lt8709 when operating as a negative boost converter. refer to this section and the appendix for further information on the design equations presented in table 4. variable definitions: v in(min) = minimum input voltage v in(max) = maximum input voltage v out = output voltage i out = output current of converter f = switching frequency dc min = power switch duty cycle at v in(max) dc max = power switch duty cycle at v in(min) v cspn = current limit voltage at dc max imon ss Cv in csp tg csn bg lt8709 8709 f08 intv cc modepg rt sync gnd en/fbin fby bias intv ee intv cc v c isp isn v out C12v4.5a Cv in C4.5v to C9v Cv in l1 2.2h mp mn c in1 330f 2.2f c out1 100f2 r in2 10k 2.2f c in2 100f2 r t 118k 100k 2m r in1 13.3k r sense1 r sense2 7m ? l2 2.2h ? r fby 130k r c 37.4k c out2 330f + 68nf 470nf c c 2.2nf c f 100pf + 2.2f c1 22f Cv in 0.47f d1 499 downloaded from: http:///
lt 8709 21 8709fa for more information www.linear.com/lt8709 8709 f09 gnd gnd Cv in Cv in Cv in Cv in r in1 r in2 (optional) en/fbin 1.7v 1.3v ? + 1.607v v c 51.5k 17.6aat 1.607v ea3 chip enable en/fbn logic active mode setting the output voltage regulation in most cases the lt8709 output voltage is set by connect- ing an external resistor ( r fby ) from the converters output, v out , to the fby pin. the equations below determine r fby : r fby = |v out | C1.234v 83.5a negative output voltage r fby = v out +15.8mv 83.9a positive output voltage see the electrical characteristics for tolerances on the fby regulation voltage and current. setting the input voltage regulation or undervoltage lockout a resistor divider between C v in and gnd, connected to the en/fbin pin, provides a means to regulate the input voltage or to create an undervoltage lockout function. referring to error amplifier ea3 in the block diagram, when en/fbin is lower than the 1.607 v reference, v c is pulled low. for example, if the negative input voltage is provided by a relatively high impedance source ( e.g. a solar panel) and the current draw pulls the magnitude of the input voltage below a preset limit, v c will be reduced, thus reducing current draw from the input supply and limit - ing the input voltage drop. note that using this function in forced continuous mode ( mode pin low) can result in current being drawn from the output and forced into the input. if this behavior is not desired then set the mode pin high to prevent reverse current flow.to set the minimum or regulated input voltage use: | v in(min C reg) |=1.607v ? 1+ r in1 r in2 ?? ? ?? ? +17.6a ?r in1 r in1 = | v in(minCreg) | C1.607v 1.607v r in2 ?? ? ?? ? +17.6a where r in1 and r in2 are shown in figure 9. for increased accuracy, set r in2 10 k. the resistor r in2 is optional, but applications information figure 9. configurable uvlo is recommended to be used to increase the accuracy of the input voltage regulation by making the r in1 current much higher than the en/fbin pin current.this same technique can be used to create an undervoltage lockout if the lt8709 is not in forced continuous mode. when in discontinuous mode, forcing v c low will stop all switching activity. note that this does not reset the soft start, therefore resumption of switching activity will not be accompanied by a soft-start. note that at start-up, the minimum voltage on en/fbin must exceed 1.7 v ( typical) to begin a soft-start cycle. afterwards, the en/fbin voltage can drop below 1.7 v and the input can be regulated such that the en/fbin voltage is at ~1.607 v. so the equation below gives the start-up input voltage for a desired input regulation voltage: | v in(start-up) |= 1.7v 1.607v ?|v in(min C reg) |+0.78a ?r in1 output current monitoring and limiting (r sense2 and isp-isn and imon pins) the lt8709 has an output current monitor circuit that can be used to monitor and/or limit the output current. the current monitor circuit works as shown in figure 10. if it is not desirable to monitor and limit the output current, simply connect the imon pin to the chip ground i.e ., C v in . note that the current sense resistor connected to the isp and isn pins must still be used, and the value should follow the guidelines in the next couple sections. downloaded from: http:///
lt 8709 22 8709fa for more information www.linear.com/lt8709 the current through r sense 2 is the sensed current through mp which turns on and off every clock cycle. since the current through r sense2 is chopped, a filtering capacitor between the imon and C v in pins is needed to filter the volt - age at the imon pin before heading to ea2. given below is the equation to calculate the required imon pin capacitance : c imon 100a ?dc max 5mv ? f where dc max is the maximum duty cycle of the converters application ( with minimum input magnitude) and f is the switching frequency.to prevent start-up issues, the imon capacitor should charge up faster than the ss capacitor. it is recommended to size the ss capacitor about 5 x greater than the imon capacitor.output current monitoring the voltage at the imon pin is a gained up version of the voltage seen across the isp and isn pins. given below are the equations relating the r sense2 current to the imon pin voltage. assume that the current through r sense2 is of steady state and that its time average is approximately equal to the converters load current: v imon =11.9 ? i rsense2(ave) ? r sense2 +51.8mv ( ) i out i sense2(ave) = v imon 11.9 ? 51.8mv ?? ? ?? ? r sense2 output current limiting as shown in figure 10, imon voltages exceeding 1.213 v (typical) cause the v c voltage to reduce, thus limiting the inductor current. this voltage on imon corresponds to an average voltage of 50 mv across r sense2 . the equation below is used to select the r sense2 resistor for limiting the output current at steady state: r sense2 = 50mv i out(limit) if it is not desirable to limit the output current, size r sense 2 by setting i out ( limit ) 60% higher than the maximum output current of the converter. this current sense resistor is needed if using the synchronous pfet in the converter. when the pfet is replaced with a schottky power diode, then r sense2 is not needed if output current limiting or monitoring isnt required. note that if the intv ee ldo is in uvlo and ss > 1.8 v ( typi- cal), then the reference voltage at ea2 reduces to 916 mv, and the output current is limited to about half its set value. output overcurrent as shown in figure 10, a comparator monitors the voltage at the imon pin and triggers a reset condition if the imon pin voltage exceeds 1.38 v ( typical). this corresponds to an average voltage of 63.6 mv ( typical) across the isp and isn pins: i out(overcurrent) = 63.6mv r sense2 i out(overcurrent) =1.27 ?i out(limit) applications information figure 10. output current monitor and control 8709 f10 isn r sense2 mp 51.8mv ? + 1.213v 11.9k 1.38v over current voltages are referred to Cv in v c Cv in Cv in Cv in Cv in ? + ea2 Cv in imon c imon isp tg ? + + ? 1ma/v a7 downloaded from: http:///
lt 8709 23 8709fa for more information www.linear.com/lt8709 reverse current applications (mode pin low) when the forced continuous mode is selected ( mode pin low), inductor current is allowed to reverse directions and flow from the output side to the input side. this can lead to current sinking from the output and being forced into the input. the reverse current is at a maximum magnitude when v c is lowest. the graph of maximum current limit vs duty cycle ( csp ? csn) in the typical performance characteristics section can help to determine the maximum reverse current capability. the imon pin voltage will indicate negative inductor currents. note that the imon voltage is only accurate if the dynamic input of the output current sense amp stays within C51.8mv to 500mv. if the inductor current goes more negative than C300 mv as sensed by r sense2 , the external pfet will turn off, and the inductor current will start going more positive. input overvoltage protection whenever the mode pin is low to allow current to flow from output to input, it is strongly recommended to add a couple external components to protect the input from overvoltage as shown in figure 11 below. with either approach, as C v in approaches the ovp point, the mode pin approaches the mode fcm threshold (1.224 v typical) and the lt8709 won 't allow reverse current flow, preventing Cv in from going below the ovp point. capacitor charging when the application is to charge a bank of capacitors such as supercaps, the charging current is set by r sense 2 . switch current limit (r sense1 and csp-csn pins) the external current sense resistor ( r sense1 ) sets the maximum peak current though the external nfet switch (mn). the maximum voltage across r sense1 is 50 mv (typical) at very low switch duty cycles, and then slope compensation decreases the current limit as the duty cycle increases ( see the max current limit vs duty cycle ( csp- csn) plot in the typical performance characteristics). the equation below gives the switch current limit for a given duty cycle and current sense resistor ( find v cspn at the operating duty cycle in the plot mentioned). i sw(limit) = v cspn r sense1 to provide a desired load current for any given application, r sense1 must be sized appropriately. the switch current will be at its highest when the input voltage magnitude is at the lowest of its range. the equation below calculates r sense1 for a desired output current: r sense1 0.74 ? ? v cspn i out ? 1Cdc max ( ) ? 1C i ripple 2 ?? ? ?? ? where = conversion efficiency (assume ~90%) v cspn = max current limit voltage (see max current limit vs duty cycle (csp-csn) plot in the typical performance characteristics) i out = converter load current dc max = switching duty cycle at minimum magnitude v in ( see power switch duty cycle in appendix ) i ripple = peak - to - peak inductor ripple current percent - age at minimum magnitude v in ( recommended to use 25%) applications information figure 11. input overvoltage protection 8709 f11 mode or Cv in v in_ovp = C(v z + 1.224v) v in_ovp = C1.224v ? gnd mode Cv in gnd 1k r ovp1 r ovp2 1+ r ovp2 r ovp1 ?? ?? downloaded from: http:///
lt 8709 24 8709fa for more information www.linear.com/lt8709 current sense filtering certain applications may require filtering of the inductor current sense signals due to excessive switching noise that can appear across r sense1 and/or r sense2 . higher operating voltages, higher values of r sense , and more capacitive mosfets will all contribute additional noise across r sense when mosfets transition. the csp/csn and/or the isp/isn sense signals can be filtered by add- ing one of the rc networks shown in figure 12. the filter shown in figure 12 a filters out differential noise, whereas the filter in figure 12 b filters out differential and common mode noise at the expense of an additional capacitor and approximately twice the capacitance value . it is recom - mended to kelvin connect the C v in sides of the filter caps directly to the paddle of the lt8709 if using the filter in figure 12 b . the filter network should be placed as close as possible to the lt8709. resistors greater than 10 should be avoided as this can increase the offset volt - ages at the csp/csn and isp/isn pins . the rc product should be kept less than 30 ns, which is simply the total series r (5.1+5.1 in this case) times the equivalent capacitance seen across the sense pins (2.2 nf for figure 12a and 2.35nf for figure 12b). switching frequency the lt8709 runs with a constant frequency between 100khz and 750 khz. the frequency can be set using the internal oscillator or can be synchronized to an external clock source. selection of the switching frequency is a trade-off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. for high power applications, consider operating at lower frequencies to minimize mosfet heating from switch- ing losses. to use the on-chip oscillator, the switching frequency can be set by placing an appropriate resistor from the rt pin to C v in , the chip ground and tying the sync pin to C v in , the logic low. the frequency can also be synchronized to an external clock source driven into the sync pin, as long as the logic levels appearing at the sync pin are relative to the chip ground ( i.e ., C v in ). the following sections provide more details. oscillator timing resistor (r t ) the operating frequency of the lt8709 can be set by the internal free-running oscillator. when the sync pin is driven low (< 0.4 v), the frequency of operation is set by a resistor from the rt pin to C v in . the oscillator frequency is calculated using the following formula: f osc = 35,880 r t +1 ( ) where f osc is in khz and r t is in k. conversely, r t ( in k) can be calculated from the desired frequency ( in khz) using: r t = 35,880 f osc C 1 clock synchronizationwith proper logic levels, an external source can set the operating frequency for lt8709 by providing a digital clock signal into the sync pin ( r t resistor still required). that way, the lt8709 will operate with this overriding sync clock frequency. the lt8709 will revert to its internal free - running oscillator clock when the sync pin is driven to logic low, i.e ., below 0.4 v for a few free - running clock periods . applications information figure 12 a . differential rc filter on csp / csn and / or isp / isn pins figure 12b. differential and common mode rc filter on csp/csn and/or isp/isn pins 8709 f012a r sense1 , r sense2 2.2nf 5.15.1 csp or isp lt8709 csn or isn 8709 f012b r sense1 , r sense2 Cv in 4.7nf 5.15.1 csp or isp lt8709 csn or isn 4.7nf downloaded from: http:///
lt 8709 25 8709fa for more information www.linear.com/lt8709 driving sync high, i.e ., 1.5 v for an extended period of time effectively stops the operating clock and prevents latch sr1 from becoming set ( see block diagram). as a result, the switching operation of the lt8709 will stop. the duty cycle of the sync signal must be between 20% and 80% for proper operation. also, the frequency of the sync signal must meet the following two criteria: 1. sync may not toggle outside the frequency range of 100khz to 750khz. 2. the sync frequency can always be higher than the free - running oscillator frequency ( as set by the r t resistor), f osc , but should not be less than 75% of f osc . after sync begins toggling, it is recommended that switch - ing activity is stopped before the sync pin stops toggling. excess negative inductor current can result when sync stops toggling as the lt8709 transitions from the external sync clock source to the internal free-running oscillator clock. switching activity can be stopped by driving the en/fbin pin low. level shifter circuits it is often the case that the user has a gnd referenced signal and would like to be able to externally control the part. this could include using a signal to enable the part, read the logic state of power good ( pg), or to sync the part to a clock. the following circuits below level shift the input signal with respect to C v in to achieve these functions . ldo regulators the lt8709 has two linear regulators to run the bg and tg gate drivers. the intv cc ldo regulates to 6.3 v ( typical) above the C v in pin, and the intv ee regulator regulates 6.18v (typical) below the bias pin. intv cc ldo regulator the intv cc ldo is used as the top rail for the bg gate driver of the primary switch, which is an n-type power mosfet with its source connected to the chip ground (i.e ., C v in ) in any applications of the lt8709. the intv cc ldo is also used as the top rail for the tg gate driver for applications in which bias and intv ee are tied to intv cc and C v in , respectively. an external capacitor of 2.2 f or greater must be placed from the intv cc pin to C v in . the uvlo threshold on intv cc is 4 v ( typical), and the lt8709 will be in reset until the ldo comes out of uvlo. applications information 8709 f013a 1k en/fbin en/fbin_ext lt8709 Cv in Cv in 20k 8709 f013b sync sync_ext gnd lt8709 Cv in Cv in 100k 0.1f 8709 f013c intv cc pg lt8709 Cv in v dd Cv in 200k 20k 10k 100k pg figure 13a. level shifter circuit for en/fbin figure 13b. level shifter circuit for sync figure 13c. level shifter circuit for pg downloaded from: http:///
lt 8709 26 8709fa for more information www.linear.com/lt8709 the intv cc ldo can run from gnd or bias and will minimize power losses by intelligently selecting the lower voltage one as long as both are at a high enough voltage above C v in . for example, the following is a plot that shows an inverting application where v out / bias is regulated to 5 v while C v in starts at C10 v and ramps to C5 v; and indicates that intv cc is regulated from gnd or bias. it should be noted that all voltages in the plot are relative to Cv in . overcurrent protection circuitry typically limits the maxi- mum current draw from the ldo to 125 ma and 65 ma when running from gnd and bias respectively. when intv cc is below ~3.5 v during start-up or an overload condition, the typical current limit is reduced to 25 ma when running from either gnd or bias. if the selected input voltage is greater than 20 v ( typical), then the current limit of the ldo reduces linearly with input voltage to limit the maximum power in the intv cc pass device. see the intv cc current limit vs gnd or bias plot in the typical performance characteristics. if the die temperature exceeds 175c (typical), the current limit of the ldo drops to 0. power dissipated in the intv cc ldo should be minimized to improve efficiency and prevent overheating of the lt8709. the current limit reduction with input voltage circuit helps prevent the part from overheating, but these guidelines should be followed. the maximum current drawn through the intv cc ldo occurs under the following conditions: 1. large ( capacitive) mosfets being driven at high frequencies. applications information figure 14. intv cc input voltage selection 2. the converters switching-node voltage (| v in | for negative buck , | v in | + v out for negative inverter, or |v in | + | v out | for negative boost or buck-boost) is high, thus requiring more charge to turn the mosfet gates on and off. in general, use appropriately sized mosfets and lower the switching frequency for higher voltage applications to keep the intv cc current at a minimum. intv ee ldo regulator the bias and intv ee voltages are used for the top and bottom rails of the tg gate driver respectively. an external capacitor of 2.2 f or greater must be placed between the bias and intv ee pins. the uvlo threshold on the regulator ( bias-intv ee ) is 3.42 v ( typical) as long as the bias voltage is greater than ~3.36 v. the tg pin can begin switching after the intv ee regulator comes out of uvlo. for positive output converters, bias must be tied to the converters output voltage. for a negative buck or negative buck-boost converter, bias must connect to gnd. for a negative boost converter, bias must tie to intv cc , and intv ee ties to C v in . in the third case, the voltage of the intv ee regulator is driven to the intv cc voltage of 6.3 v and hence the tg gate driver will have C v in referred levels of 0v and 6.3v. overcurrent protection circuitry typically limits the maxi - mum current draw from the regulator to 65 ma. if the bias voltage is greater than 20 v ( typical), then the current limit of the regulator reduces linearly with input voltage to limit the maximum power in the intv ee pass device. see the intv ee current limit vs bias plot in the typical performance characteristics. if the die temperature exceeds 175c ( typical), the current limit of the ldo drops to zero. the thermal guidelines from the intv cc ldo regulator section apply to the intv ee regulator as well. non-synchronous converter it may be desirable in some applications to replace the external pfet with a schottky diode to make a non- synchronous converter. one example would be a high 8709 f14 time selected input voltage v bias C v Cvin v gnd C v Cvin gnd gnd bias bias 10v 13v 10.8v 15v 8.5v 5v 8v downloaded from: http:///
lt 8709 27 8709fa for more information www.linear.com/lt8709 output voltage application because the voltage drop across the rectifier has a small effect on the efficiency of the converter. in fact, replacing the pfet with a schottky may result in higher efficiency because the lt8709 doesn t have to supply gate drive to the pfet. figure 15 shows the recommended connections for using the lt8709 as a non - synchronous negative buck - boost converter, however the same concept can be used for any other converter. note that the mode pin must be tied high if using the lt8709 as a non-synchronous converter or else the out - put might not be regulated at light load. also, the tg pin must be left floating or permanent damage could occur to the tg gate driver. if it is not desirable to monitor and/ or control the output current, r sense2 is not needed and simply tie the isp and isn pins to gnd. the imon pin can be left floating or connected to C v in . the bias and intv ee pins can tie to C v in if the dual input feature of the intv cc ldo is not needed and the input voltage magnitude stays above 4.5v. layout guidelines for applications general layout guidelines ? to optimize thermal performance, solder the exposed pad of the lt8709 to the chip ground plane ( i.e ., C v in ) with multiple vias around the pad connecting to ad- ditional Cv in planes. ? high speed switching path ( see specific topology below for more information) must be kept as short as possible . ? the fby, v c , imon, and rt components should be placed as close to the lt8709 as possible, while being far away as practically possible from switching nodes. the C v in node/plane for these components should be separated from the switch current path. ? place bypass capacitors for the gnd and bias pins (c gnd and c bias ) as close as possible to the lt8709. ? place bypass capacitors for the intv cc and intv ee pins (c vcc and c vee ) as close as possible to the lt8709. ? the load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. applications information figure 15. nonsynchronous negative buck-boost imon ss Cv in csp tg csn bg lt8709 8709 f15 intv cc modepg rt sync gnden/fbin fby bias intv ee v c isp isn v out Cv in Cv in r sense2 d1 ** + + ** optional - if output current sensing isnt necessary, remove r sense2 ; connect isp and isn pins and d1 cathode to gnd; and connect imon pin to Cv in . ** downloaded from: http:///
lt 8709 28 8709fa for more information www.linear.com/lt8709 negative inverting topology specific layout guidelines ? keep length of loop ( high speed switching path) govern - ing c in2 , r sense1 , mn, mp, r sense2 , c out1 , and return through ground as short as possible to minimize parasitic inductive spikes at the switch node during switching. negative buck-boost topology specific layout guidelines ? keep length of loop ( high speed switching path) gov - erning c in , r sense1 , mn, c1, mp, r sense2 , and return through ground as short as possible to minimize parasitic inductive spikes at the switch node during switching. applications information negative buck topology specific layout guidelines ? keep length of loop ( high speed switching path) govern - ing r sense1 , mn, mp, c in and return through C v in as short as possible to minimize parasitic inductive spikes at the switch node during switching. figure 16c. negative buck-boost pcb layout figure 16a. inverting converter pcb layout figure 16b. negative buck converter pcb layout lt8709 l1 8709 f16a v out Cv in c out1 c in1 c out2 r sense2 r sense1 gnd c in2 gnd gnd mp mn lt8709 r sense1 Cv in r sense2 c in c in c out Cv out 8709 f16b l1 mn gnd gnd mp lt8709 8709 f16c c out c in Cv out Cv in c in r sense2 r sense1 mn mp l1l2 gnd gnd c1 downloaded from: http:///
lt 8709 29 8709fa for more information www.linear.com/lt8709 applications information figure 16d. negative boost pcb layout figure 17. suggested routing and connections of csp/csn and isp/isn lines negative boost topology specific layout guidelines ? keep length of loop ( high speed switching path) govern - ing r sense1 , mn, c1, mp, r sense2 , and return through Cv in as short as possible to minimize parasitic inductive spikes at the switch node during switching. lt8709 8709 f16d c in c1 Cv in Cv out c out r sense1 c2 d1 r1 r sense2 mn mp gnd gnd l2 l1 current sense resistor layout guidelines? route the csp / csn and isp / isn lines differentially ( close together) from the chip to the current sense resistors as shown in figure 17. ? place the vias that connect to csp/csn and isp/isn lines directly at the inner current sense pads of the current sense resistors as shown in figure 17. thermal considerations overview the components on the board that dissipate the most heat are the power switches , ( i.e., mn and mp), the power inductor, and the lt8709 ic. it is imperative that a good thermal path be provided for these components to dissipate the heat generated within the packages. this can be accomplished by taking advantage of the thermal pads on the underside of the packages. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from each of these components and into a copper plane with as much area as possible. for the case of the power switches, the copper area of the drain connections shouldnt be too big as to create a large emi surface that can radiate noise around the board. power mosfet loss and thermal calculations the lt8709 requires two external power mosfets, an nfet switch for the bg gate driver and a pfet switch for the tg gate driver. important parameters for estimating the power dissipation in the mosfets are: 1. on-resistance (r dson ) 2. gate-to-drain charge (q gd ) 3. pfet body diode forward voltage (v bd ) 4. v ds of the fets during their off-time 5. switch current (i sw ) 6. switching frequency (f) the power loss in each power switch has a dc and ac term. the dc term is when the power switch is fully on, and the ac term is when the power switch is transitioning from on-off or off-on. the following applies for both the nfet and pfet power switches. for a negative buck converter, the average cur - rent through the mosfet ( i sw ) during its on-time is the same as the average output current; and the magnitude of the drain-to-source voltage, v ds , during its off-time is | v in |. for a negative buck-boost or inverting or boost application, the average current through each mosfet (i sw ) during its on-time, is the sum of the average input current and the output current. the | v ds | voltage during the off-time is approximately | v in | + | v out |. during the 8709 f17 to current sense pins r sense1,2 downloaded from: http:///
lt 8709 30 8709fa for more information www.linear.com/lt8709 non-overlap time of the gate drivers, the peak and valley inductor current is flowing through the body diode of the pfet. given below are the equations for the power loss in mn and mp. p mosfet =p i 2 r +p switching p mn =i n 2 ?r dson + v ds ?i n ? f ? t rf +p rr C n p mp =i p 2 ?r dson + v bd ? i pk + i vy 1.6 ?? ? ?? ? ? f?140ns+p rr C p i sw = i out (1Cdc) ; i pk =i sw + i ripple 2 ; i vy =i sw C i ripple 2 i n = dc ? i sw 2 + i ripple 2 12 ?? ? ?? ? i p = 1Cdc ( ) ? i sw 2 + i ripple 2 12 ?? ? ?? ? p rr C n v ds ?i rr ? t rr ? f 2 p rr C p v ds ?i rr ? t rr ? f 2 where: f = switching frequency i n = nfet rms current i p = pfet rms current t rf = average of the rise and fall times of the nfets drain voltage i sw = average switch current during its on-time i pk = peak inductor current i vy = valley inductor current i ripple = inductor ripple current dc = switch duty cycle ( see power switch duty cycle section in appendix) v bd = pfet body diode forward voltage at i sw p rr-n = nfet i 2 r loss term from the pfet body diode reverse recovery p rr-p = pfet body diode reverse recovery power loss i rr = current needed to remove the pfet body diode charge t rr = reverse recovery time of pfet body diode applications information typical values for t rf are 10 ns to 40 ns depending on the mosfet capacitance and drain voltage. in general, the lower the q gd of the mosfet, the faster the rise and fall times of its drain voltage. for best calculations, measure the rise and fall times in the application. pfet body diode reverse recovery power loss is depen- dent on many factors and can be difficult to quantify in an application. in general, this power loss increases with higher v ds and/or higher switching frequency. chip power and thermal calculations power dissipation in the lt8709 chip comes from three primary sources: the intv cc ldo, intv ee ldo, and input quiescent current. the average current through each ldo is determined by the gate charge of the power switches, mn and mp, and the switching frequency. given below are the equations for calculating the chip power loss fol- lowed by examples. negative buck, buck-boost and inverting converters: the intv cc ldo primarily supplies voltage for the bg gate driver. the bias and intv ee voltages supply the top and bottom rails of the tg gate driver respectively. the chip q current comes from the higher of gnd and bias, referred to C v in . given below are the chip power equations for a negative buck, buck-boost or inverting converter: p vcc = 1.04 ? q mn ? f ? v select p vee1 = q mp ? f ? v bias p vee2 = 3.1ma ? (1 C dc) ? v bias p q = 4ma ? v max where: f = switching frequency dc = switch duty cycle ( see power switch duty cycle section in appendix) q mn = total gate charge of nfet power switch ( mn ) at 6.3v gs q mp = total gate charge of pfet power switch ( mp ) at 6.18v sg v select = intv cc ldo selected input voltage, gnd or bias (see ldo regulators section) v max = higher of gnd and bias. downloaded from: http:///
lt 8709 31 8709fa for more information www.linear.com/lt8709 applications information negative boost converter : since bias connects to intv cc and intv ee connects to C v in ( see typical applications), all the chip power comes from the gnd pin. the intv cc ldo primarily supplies voltage for both the bg and tg gate drivers. the chip q current comes from gnd. for consistency, the power thats needed to run the tg gate driver is still labeled as p vee even though the power is coming from intv cc . given below are the chip power equations for a negative boost converter: p vcc = 1.04 ? q mn ? f ? v in p vee1 = q mp ? f ? v in p vee2 = 3.15ma ? (1 C dc) ? v in p q = 5.5ma ? v in where: f = switching frequency v in = the voltage difference between gnd and C v in pins dc = switch duty cycle ( see power switch duty cycle section in appendix) q mn = total gate charge of nfet power switch ( mn) at 6.3v gs q mp = total gate charge of pfet power switch ( mp) at 6.3v sg chip power calculations example table 5 calculates the power dissipation of the lt8709 for a 250khz , C16 v to C30 v input to C12 v /8.5 a buck application when v in is C24 v. from p chip in table 5, the die junc- tion temperature can be calculated using the appropriate thermal resistance and worst-case ambient temperature: t j = t a + ja ? p chip where t j = die junction temperature, t a = ambient tem- perature and ja is the thermal resistance from the silicon junction to the ambient air. the published ja value is 38 c/w for the tssop exposed pad package. in practice, lower ja values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the layout guidelines sec - tion. for instance, a ja value of ~22 c/w was consistently achieved when board layout was optimized as per the suggestions in the layout guidelines section. thermal lockout if the die temperature reaches ~175 c, the part will go into reset, so the power switches turn off, the soft-start capacitor will be discharged and the current limit of the intv cc and intv ee regulators drop to 0. the lt8709 will come out of reset when the die temperature drops by ~5c (typical). table 5. power calculations example for a 250 khz , ?16 v in to ?30 v in to ?12 v out /8.5 a buck (? v in = ?24 v , mn = bsc026 n 04ls and mp = fdd4141) definition of variables equation design example value dc = switch duty cycle d c ? v out v in dc ? C12vC24v dc ? 50% p vcc = intv cc ldo power driving the bg gate driver q mn = nfet total gate charge at v gs = 6.3v f = switching frequency v select = ldo chooses gnd p vcc = 1.04 ? q mn ? f ? v select p vcc = 1.04 ? 20 nc ? 250 khz ? 24 v p vcc = 125 mw p vee1 = intv ee ldo power driving the tg gate driver q mp = pfet total gate charge at v sg = 6.18v p vee 1 = q mp ? f ? v bias p vee 1 = 24 nc ? 250 khz ? 24 v p vee 1 = 144 mw p vee2 = additional tg gate driver power loss p vee 2 = 3.1 ma ? (1 C dc ) ? v bias p vee 2 = 3.1 ma ? (1C 0.5) ? 24 v p vee 2 = 37.2 mw p q = chip bias loss v max = higher voltage of ( v gnd C v C vin ) and ( v bias C v C vin ) p q = 4 ma ? v max p q = 4 ma ? 24 v p q = 96 mw p chip = 0.4021 w downloaded from: http:///
lt 8709 32 8709fa for more information www.linear.com/lt8709 appendix power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the external power nfet ( mn in the block diagram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = t p Cminofftime ( ) t p ?100% where t p is the clock period and minofftime ( found in the electrical characteristics) is a maximum of 480ns. conversely, the external power nfet ( mn in the block diagram) cannot remain off for 100% of each clock cycle, and will turn on for a minimum on time ( minontime) when in regulation. this minontime governs the minimum al - lowable duty cycle given by: dc min = (minontime) t p ?100% where t p is the clock period and minontime ( found in the electrical characteristics) is a maximum of 420ns.the application should be designed such that the operating duty cycle is between dc min and dc max . duty cycle equations for several common topologies are given below where v mp_on is the voltage drop across the external power pfet ( mp) when it is on, and v mn_on is the voltage drop across the external power nfet ( mn) when it is on.for the negative buck topology (see figure 5): dc Cbuck ? | v out | +v mp_on | v in |+v mp_on C v mn_on for the negative inverting topology (see figure 6): dc Cinverter ? v out + v mp_on | v in |+v out + v mp_on C v mn_on for the negative buck-boost topology (see figure 7): dc CbuckCboost ? | v out |+ v mp _ on | v in |+| v out |+ v mp _ on C v mn _ on for the negative boost topology (see figure 8): dc Cboost ? | v out | C | v in |+ v mp _ on | v out |+ v mp _ on C v mn _ on the lt8709 can be used in configurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode ( mode pin must be high) so that the effective duty cycle is reduced.inductor selection for high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. also to improve efficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr ( copper - wire resistance ) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturat- ing. note that in some applications, the current handling requirements of the inductor can be lower, such as in the negative buck-boost topology where each inductor carries a fraction of the total switch current. molded chokes or chip inductors do not have enough core area to support peak inductor currents in the 5 a to 15 a range. to minimize radiated noise, use a toroidal or shielded inductor. see table 6 for a list of inductor manufacturers. table 6. inductor manufacturers coilcraft mss1278, xal1010, and msd1278 series www.coilcraft.com cooper bussmann dr127, drq127, and hcm1104 series www.cooperbussmann.com vishay ihlp series www.vishay.com wrth we-hci and we-cfwi series www.we-online.com minimum or maximum inductance although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are three conditions that limit the minimum or maximum inductance ; (1) providing adequate load current, and (2) avoiding sub - harmonic oscillation, and (3) supplying a minimum ripple current to avoid false tripping of the current comparator. downloaded from: http:///
lt 8709 33 8709fa for more information www.linear.com/lt8709 appendix adequate load current small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. in order to provide adequate load current, l should be at least : l Cbuck | v in | C | v out | ( ) ?dc 2 ? f ? v cspn r sense1 Ci out ?? ? ?? ? l Cinverter | v in | ? dc 2 ? f ? v cspn r sense1 C | v out |?i out | v in | ? Ci out ?? ? ?? ? l Cbuck_boost | v in | ? dc 2 ? f ? v cspn r sense1 C | v out | ? i out | v in | ? Ci out ?? ? ?? ? l Cboost | v in | ? dc 2 ? f ? v cspn r sense1 C | v out | ? i out | v in | ? Ci out ?? ? ?? ? where l -buck or l -inverter = l 1 for the negative buck or invert- ing topologies (see figures 5 and 6)l -buck-boost or l -boost = l 1 = l 2 for coupled dual inductor topologies (see figures 7 and 8)l -buck-boost or l -boost = l 1 || l 2 for uncoupled dual inductor topologies (see figures 7 and 8)dc = switch duty cycle (see previous section) v cspn = current limit voltage at the operating switch duty cycle ( see max current limit vs duty cycle ( csp ? csn ) plot in the typical performance characteristics) r sense1 = current sense resistor connected across the csp-csn pins (see block diagram) = power conversion efficiency (assume ~90%) f = switching frequencyi out = maximum output current negative values of inductance from above equations indicate that the output load current, i out , exceeds the switch current limit capability of the converter. decrease r sense1 to increase the switch current limit. avoiding sub-harmonic oscillations the lt8709s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the in - ductance exceeds a minimum value. in applications that operate with duty cycles greater than 50%, the inductance must be at least: l min | v in | ?r sense1 ?(2 ?dc C 1) 40m?dc ? f ?(1Cdc) l min r sense1 ?| v in |?(2 ?dc C 1) f ? 40mv ?dc where l min = l 1 for single inductor topologies ( see figures 5 and 6). note: for the negative buck , | v in | C | v out | replaces |v in |. l min = l 1 = l 2 for coupled dual inductor topologies (see figures 7 and 8)l min = l 1 || l 2 for uncoupled dual inductor topologies (see figures 7 and 8) maximum inductance excessive inductance can reduce ripple current to levels that are difficult for the current comparator ( a6 in the block diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max | v in | ? r sense1 ?dc 3mv ? f for negative boost, buck-boost and inverting converters for negative buck converters downloaded from: http:///
lt 8709 34 8709fa for more information www.linear.com/lt8709 appendix where l max = l 1 for single inductor topologies ( see figures 5 and 6). note: for the negative buck , | v in | C | v out | replaces |v in |. l max = l 1 = l 2 for coupled dual inductor topologies (see figures 7 and 8)l max = l 1 || l 2 for uncoupled dual inductor topologies (see figures 7 and 8) inductor current rating the inductor(s) must have a rating greater than its ( their) peak operating current to prevent inductor saturation, which would result in efficiency losses. the maximum inductor current ( considering start-up and steady-state conditions) is given by: i l_peak = 54mv C 16mv ?dc 2 r sense1 + v in ? t min_prop l where i l_peak = peak inductor current in l 1 for a single inductor topologies or the sum of the peak inductor currents for dual inductor topologies. t min_prop = 100 ns ( propagation delay through the current feedback loop). note that these equations offer conservative results for the required inductor current ratings. the current ratings could be lower for applications with light loads, and if the ss capacitor is sized appropriately to limit inductor currents at start-up.for wide input voltage range applications, as the input volt - age increases, the max peak inductor current also increases due to the duty cycle decreasing. it is recommended to utilize the output current limiting feature to reduce the max peak inductor current given by the following equation: i l_peak = v ispn r sense2 ? (1Cdc) + v l ? dc 2 ? f ?l where...v ispn = 57 mv max for negative buck, inverting and buck- boost converters and 60 mv max for the negative boost converter. note that v l represents the voltage across the inductor and is equal to | v in | C | v out | for a negative buck converter and | v in | for a negative boost, buck-boost, or inverting converter. rc damping network for dual inductor topologies with single inductors two discrete inductors shown in figure 18 can be used when the lt8709 is configured for the negative buck - boost or negative boost topologies with a few requirements. 1. size the flying capacitor c1 4.7f 2. calculate the value of the damping resistor and ensure that r damp 3 to limit power dissipation 3. calcuate c damp it should be noted that the value of c1 may need to be adjusted if r damp cannot be made below or close to 3. power mosfet selection the lt8709 requires two external power mosfets, an nfet switch for the bg gate driver and a pfet switch for the tg gate driver. it is important to select mosfets for optimizing efficiency. for choosing an nfet and pfet, the important device parameters are: 1. breakdown voltage (bv dss ) 2. gate threshold voltage (v gsth ) 3. on-resistance (r dson ) 4. total gate charge (q g ) 5. turn-off delay time (t d(off) ) 6. package has exposed paddle as heat sink figure 18. rc damp network for single inductors 8709 f018 r damp c damp c1 l1 l2 c damp > 2c1 r damp l1+l2 c1 downloaded from: http:///
lt 8709 35 8709fa for more information www.linear.com/lt8709 appendix the drain-to-source breakdown voltage of the nfet and pfet power mosfets must exceed: ? bv dss > |v in | for negative buck converters ? bv dss > | v in | + | v out | for negative boost, buck-boost, or inverting converters if operating close to the bv dss rating of the mosfet, check the leakage specifications on the mosfet because leakage can decrease the efficiency of the converter. the nfet and pfet gate-to-source drive is approximately 6.3v and 6.18 v respectively, so logic level mosfets are required. the bg gate driver can begin switching when the intv cc voltage exceeds ~4 v, so ensure the selected nfet is in the triode region of operation with 4 v of gate- to-source drive to prevent possible damage to the nfet. the tg gate driver can begin switching when the bias- intv ee voltage exceeds ~3.42 v, so it is optimal that the pfet be in the triode region of operation with 3.42 v of gate-to-source drive. however, the pfet is less likely to be damaged if its not operating in the triode region since the drain-to-source voltage is clamped by its body diode during the nfets off-time. having said that, try to choose a pfet with a low body diode reverse recovery time to minimize stored charge in the pfet. the stored charge in the pfet body diode is removed when the nfet switch turns on and can lead to a reduction in efficiency especially in applications where the v ds of the pfet ( during off-time) is high. for these applications, it may be beneficial to put a schottky diode across the pfet to reduce the amount of charge in the pfet body diode. in applications where the output voltage is high in magnitude, it is recommended to replace the pfet with a schottky diode since the converter may be more efficient. power mosfet on-resistance and total gate charge go hand-in-hand and are typically inversely proportional to each other; the lower the on-resistance, the higher total gate charge. choose mosfets with an on-resistance to give a voltage drop to be less than 300 mv at the peak current. at the same time, choose mosfets with a lower total gate charge to reduce lt8709 power dissipation and mosfet switching losses. the turn-off delay time ( t d(off) ) of available nfets is generally smaller than the lt8709s non-overlap time. however, the turn-off time of the available pfets should be checked before deciding on a pfet for a given applica- tion. the turn-off time must be less than the non-overlap time of the lt8709 or else the nfet and pfet could be on at the same time and damage to external components may occur. if the pfet turn-off delay time as specified in the data sheet is less than the lt8709 non-overlap time, then the pfet is good to use. if the turn-off delay time is longer than the non-overlap time, it doesnt necessarily mean it cant be used. it may be unclear how the pfet manufacturer measures the turn-off delay time, so it is best to measure the pfet turn-off delay time with respect to the pfet gate voltage. finally, both the nfet and pfet power mosfets should be in a package with an exposed paddle for the drain connection to be able to dissipate heat. the on-resistance of mosfets is proportional to temperature, so its more efficient if the mosfets are running cool with the help of the exposed paddle. see table 7 for a list of power mosfet manufacturers. table 7. power mosfet (nfet and pfet) manufacturers fairchild semiconductor www.fairchildsemi.com on-semiconductor www.onsemi.com vishay www.vishay.com diodes inc. www.diodes.com table 8. recommended pfets 20v si7635dp, si7633dp www.vishay.com 30v si7101dn, si7143dp www.vishay.com 40v fdd4141, si7463adp, sis443dn, si7611dn, www.fairchildsemi.com, www.vishay.com 60v si7465dp, sud19p06-60, sud50p06-15 www.vishay.com 100v fdmc86139p, si7113dn www.fairchildsemi.com, www.vishay.com input and output capacitor selection input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. a parallel combination of ca- pacitors is typically used to achieve high capacitance and low esr ( equivalent series resistance). tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. capacitors with downloaded from: http:///
lt 8709 36 8709fa for more information www.linear.com/lt8709 appendix low esr and high ripple current ratings, such as os-con, sun-con and poscap are also available. ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching noise. a minimum 2.2 f ceramic capacitor should also be placed from gnd to C v in and from bias to C v in as close to the lt8709 pins as possible. due to their excellent low esr characteristics, ceramic capacitors can significantly reduce ripple voltage and help reduce power loss in the higher esr bulk capacitors. x5r or x7r dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. many ceramic ca - pacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage.input capacitor, c in given below are the equations for calculating the capaci- tance of c in for 0.5% input voltage ripple: c in i out ? dc ? (1Cdc) f ? 0.005?| v in | c in dc 8 ?l ? f 2 ? 0.005 c in i out ?dc f ? 0.005 ? v out c in i out ?dc f ? 0.005 ? v in where: dc = switch duty cycle ( see power switch duty cycle section) l = inductance for adequate load current ( see inductor selection section) f = switching frequency keep in mind that the voltage rating of the input capacitor needs to be greater than the maximum input voltage. the equations calculate the capacitance value during steady- state operation and may need to be adjusted for desired transient response. also, this assumes no esr, so the input capacitance may need to be larger depending on the equivalent esr of the input capacitor(s).output capacitor, c out the output capacitor, c out , in a negative inverting topology has chopped current flowing through it, whereas the output capacitor in a negative buck, boost or buck-boost topology sees the inductor ripple current continuously ramping up and down. given below is the equation for calculating the capacitance of c out for 0.5% output voltage ripple: c out > i out ?dc f ? 0.005 ? v out or c out > 1Cdc 8 ?l ? f 2 ? 0.005 where: i out = maximum output current of converter dc = switch duty cycle (see power switch duty cycle section) l = inductance for adequate load current (see inductor selection section) f = switching frequency the equations calculate the capacitance value during steady-state operation and may need to be adjusted for desired transient response. also, this assumes no esr, so the output capacitance may need to be larger depending on the equivalent esr of the output capacitor(s). see table 9 for a list of ceramic capacitor manufacturers. table 9. ceramic capacitor manufacturers tdk www.tdk.com murata www.murata.com taiyo yuden www.t-yuden.com compensation ? adjustment to compensate the feedback loop of the lt8709, a series resistor capacitor network in parallel with an optional single capacitor should be connected from the v c pin to negative inverting converters negative buck, boost, buck -boost converters negative inverting converter negative buck-boost converter negative boost converter negative buck converter downloaded from: http:///
lt 8709 37 8709fa for more information www.linear.com/lt8709 figure 19c. transient response is well damped figure 19a. transient response shows excessive ringing figure 19b. transient response is better appendix Cv in . for most applications, choose a series capacitor in the range of 1 nf to 10 nf with 4.7 nf being a good starting value. the optional parallel capacitor should range in value from 47 pf to 220 pf with 100 pf being a good starting value. the compensation resistor, r c , is usually in the range of 5 k to 50 k. a good technique to compensate a new application is to use a 100 k potentiometer in place of the series resistor r c . with the series and parallel capacitors at 2.2 nf and 100 pf respectively, adjust the potentiometer while observing the transient response and the optimum value for r c can be found. figures 19 a to 19 c illustrate this process for the circuit of figure 22 with a load cur- rent stepped between 3 a and 8 a. figure 19 a shows the transient response with r c equal to 208. the phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. in figure 19 b, the value of r c is increased to 1.5 k, which results in a more damped response. figure 19 c shows the results when r c is increased further to 5.9 k. the transient response is nicely damped and the compensation procedure is complete. compensation ? theory like all other current mode switching regulators, the lt8709 needs to be compensated for stable and efficient operation. tw o feedback loops are used in the lt8709: a fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 20 shows the key equivalent elements of a negative buck converter where C v in is treated as the signal ground. because of the fast current control loop, the power stage of the ic, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier g mp and a current controlled current source g mp acts as a current source where the peak input current, i out , is proportional to the v c voltage and current sense resistor, r sense1 . note that the maximum output currents of g mp and g ma are finite. the external current sense resistor, r sense1 , sets the value of: g mp 1 6 ?r sense1 the error amplifier, g ma , is nominally about 200 mhos with a source and sink current of about 12 a and 19 a respectively. r c = 208 i load 5a/div v out 500mv/div ac-coupled i l 5a/div 200s/div 8709 f19a r c = 1.5k i load 5a/div v out 500mv/div ac-coupled i l 5a/div 200s/div 8709 f19b r c = 5.9k i load 5a/div v out 500mv/div ac-coupled i l 5a/div 200s/div 8709 f19c downloaded from: http:///
lt 8709 38 8709fa for more information www.linear.com/lt8709 appendix from figure 20, the dc gain, poles and zeros can be calculated as follows:dc gain: a dc = g ma ?r o ? g mp ?r l ? r fby2 || 1 g m ,q1 ?? ? ?? ? r fby1 + r fby2 || 1 g m ,q1 ?? ? ?? ? ? g m ,q1 ?r2 / 2 output pole: p1= 1 2 ? ?r l ?c out error amp pole: p2 = 1 2 ? ?(r o +r c )?c c error amp zero: z1= 1 2 ? ?r c ?c c esr zero: z2 = 1 2 ? ?r esr ?c out phase lead zero: z3 = 1 2 ? ?r fby1 ?c pl phase lead pole: p4 = 1 2 ? ?r fby2 || 1 g m(q1) ?c pl error amp filter pole: p5 = 1 2 ? ? r c ?r o r c +r o ?c f ,c f < c c 10 rhp zero: z4 = v in 2 ?r l 2 ? ? v out 2 ?l the current mode zero ( z3) which exists for the inverting and dual inductor topologies only, is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. using the circuit in figure 22 as an example, table 10 shows the parameters used to generate the bode plot shown in figure 21. table 10: bode plot parameters parameter value units comment r l 1.41 application specific c out 66 f application specific r esr 2 m application specific r o 350 k not adjustable c c 2200 pf adjustable c f 100 pf optional/adjustable c pl 0 pf optional/adjustable r c 5.9 k adjustable r fby1 33 k adjustable r fby2 4.99 k adjustable r2 14.5 k not adjustable v out C12 v application specific v in C24 v application specific g ma 200 mho not adjustable g mp 83.3 mho application specific g m,q1 1.8 mmho not adjustable g m,m1 1.05 mmho not adjustable l 7.3 h application specific f osc 250 khz adjustable from figure 21, the phase is C120 when the gain reaches 0 db giving a phase margin of 60. the crossover frequency is 50khz. downloaded from: http:///
lt 8709 39 8709fa for more information www.linear.com/lt8709 appendix figure 20. negative buck converter equivalent model 8709 f20 c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductance amplifier inside ic g mp : power stage transconductance amplifier g m,q1 : transconductance of q1 when conducting for Cv out g m,m1 : transconductance of m1 when conducting for +v out r c : compensation resistor r l : output resistance defined as v out /i load(max) r o : output resistance of g ma r fby1 , r fby2 : feedback resistor divider network r esr : output capacitor esr : converter efficiency (~90% at higher currents) i out i out 1:1 c f ? + ? + 1.213v reference c c r c r o v c r2 r fby1 i fby fby r fby2 v out r l r2 v bp v bn q1m1 fbx g ma g mp c pl r esr c out 1:1 figure 21. bode plot for example negative buck converter gain (db) 140100 120 8060 40 20 0 C20 phase (deg) 0C90 C45C135 C180 C225 C270 C315 C360 8709 f21 frequency (hz) 10 100 100k 1m 10k 1k 60 at 50khz gain phase downloaded from: http:///
lt 8709 40 8709fa for more information www.linear.com/lt8709 appendix figure 22. negative buck converter imon ss Cvin csp tg csn bg lt8709 8709 f22 intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isn isp v out C12v8.5a Cv in C16v to C30v Cv in l1 7.3h mp r sense2 4m mn c in1 120f 2.2f c out1 22f3 10k 2.2f c in2 10f6 143k 100k 2m 62.5k r sense1 ? 5.9 k c out2 150f + 68nf 470nf 2.2nf 100pf + 2.2f 2.2f 4.99k 33k downloaded from: http:///
lt 8709 41 8709fa for more information www.linear.com/lt8709 typical application 250khz, ?16v to ?30v input to ?12v output, negative buck converter delivers up to 8.5a output current efficiency and power loss vs load current (?v in = ?24v) transient response with 3a to 8a to 3a output load step (?v in = ?24v) imon ss Cv in csp tg csn bg lt8709 8709 ta02a intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isn isp v out C12v8.5a Cv in Cv in C16v to C30v l1 7.3h mp r sense2 4m r sense1 2m mn c in1 120f 2.2f c out1 22f3 33k4.99k 10k 2.2f c in2 10f6 l1: wrth-hci, 7.3h, 7443551730 mp: fairchild, fdd4141 mn: infineon, bsc026n04ls r sense1 : 2m, 2512 r sense2 : 4m, 2512 c in1 : 0scon, 35v, 120f, 35svpf120m c in2 : 50v, 10f, x7s, 1210 c out1 : 25v, 22f, x7r, 1812 c out2 : oscon, 16v, 150f, 16seqp150m 143k 100k 62.5k 5.9 k c out2 150f + 68nf 470nf 2.2nf 100pf + 2.2f 2.2f load current (a) 0 efficiency (%) power loss (w) 100 80 9060 40 30 7050 20 10 4.53.5 4.02.5 1.5 3.02.0 1.0 0.5 0 5 2 7 8 9 8709 ta02b 3 4 1 6 i load 5a/div v out 500mv/div ac-coupled i l 5a/div 200s/div 8709 ta02c downloaded from: http:///
lt 8709 42 8709fa for more information www.linear.com/lt8709 typical application split supply input generates 5v with up to 10a output current efficiency and power loss vs load current (v in = 12v) transient response with 3a to 8a to 3a output load step (v in = 12v) load current (a) 0 efficiency (%) power loss (w) 100 80 9060 40 30 7050 20 10 97 85 3 64 2 1 0 5 2 7 8 10 9 8709 ta03b 3 4 1 6 i load 5a/div v out 200mv/div ac-coupled i l1 + i l2 5a/div 100s/div 8709 ta03c imon ss csp bg csn tg lt8709 8709 ta03a intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isp isn v out 5v10a v in(neg) = C12v 10% v in(neg) v in(neg) l1 3.5h r sense2 3m c1 10f 2 v in(pos) = 12v 10% 2.2f c out1 100f3 10k c in1 22f3 c in2 22f3 143k 100k 2m mn2 93.1k r sense1 ? 60.4 k 10 10 mp 2 1 4.3k c out2 330f + 47nf 220nf 2.2nf 100pf 2.2f 2.2f l1, l2: wrth-cfwi, 3.5h, 74485540350 mn: infineon, bsc059n04lsg mp: fairchild, fdd4141 r sense1 : 2m, 2512 r sense2 : 3m, 2512 c in1 : 22f, 25v, 1812, x7r c in2 : 22f, 25v, 1812, x7r c1: 10f, 25v, 1210, x7r c out1 : 100f, 16v, 1210, x5r c out2 : oscon, 16v, 330f, 16seqp330m Cv in 4.7nf4.7nf ? l23.5h dc = v out v in(pos) +| v in(neg) |+v out fet bv dss > v in(pos) +| v in(neg) |+v out c1 vrating >v in(pos) downloaded from: http:///
lt 8709 43 8709fa for more information www.linear.com/lt8709 typical application 200khz, ?4.5v to ?42v input to 5v/4a output negative inverting converter efficiency and power loss vs load current transient response with 1.5a to 4a to 1.5a output load step (?v in = ?5v) imon ss Cv in csp tg csn bg lt8709 8709 ta04 intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isp isn v out 5v4a Cv in C4.5v to C42v Cv in l1 4.7h mn r sense1 r sense2 8m mp 2.2f c out1 100 f 4 10k 2.2f c in 10f6 330f 178k 100k 1.5m 4.99k 60.4 k 1 6.9k c out2 330f + 68nf 470nf 3.3nf 100pf 2.2f l1: wrth-hci, 4.7h, 7443551470 mp: vishay, sud50p06 mn: fairchild, fdms86500l r sense1 : 1.5m, 2512 r sense2 : 8m, 2512 c in1 : 10f, 50v, 1206, x5r c out1 : 100f, 6.3v, 1812, x5r c out2 : oscon, 16v, 330f, 16seqp330m + 2.2f load current (a) 0 efficiency (%) power loss (w) 100 80 9060 40 30 7050 75 3 64 2 1 0 2 8709 ta04b 3 4 1 Cv in = C12v Cv in = C12v Cv in = C5v Cv in = C5v i load 2a/div v out 200mv/div ac-coupled i l 5a/div 200s/div 8709 ta04c downloaded from: http:///
lt 8709 44 8709fa for more information www.linear.com/lt8709 typical application 400khz, negative buck-boost converter generates a ?24v/2.5a output from a ?15v to ?30v input efficiency and power loss vs load current transient response with 1a to 2.5a to 1a output load step (?v in = ?24v) imon ss csp tg csn bg lt8709 8709 ta05 intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isp isn v out C24v2.5a Cv in C15v to C30v Cv in l1 15.4h r damp c damp c1 10f mn d1 220f 2.2f c out1 10f2 l1, l2: wrth-hci, 15.4h, 7443551151 mn: infineon, bsc039n06ns d1: diodes inc, sbr12u100p5 r sense1 : 3m, 2512 r sense2 : 13m, 2512 c in : 50v, 10f, x7r, 1210 c1: 50v, 10f, x7r, 1210 r damp : 2.2, 0805 c damp : 50v, 10f, x7r, 1210 c out1 : 50v, 10f, x7r, 1210 10k 4.7f c in 10f4 88.7k 100k r sense1 3m 54.9k r sense2 13m 274k l2 15.4h 60.4 k c out2 330f 68nf 470nf 3.3nf 100pf + 2.2f 4.7f 10f 3 2.2 Cv in load current (a) 0 efficiency (%) power loss (w) 100 80 9060 40 30 7050 75 3 64 2 1 0 1 8709 ta05b 2 1.5 2.5 0.5 Cv in = C15v Cv in = C15v Cv in = C24v Cv in = C24v i load 2a/div v out 500mv/div ac-coupled i l1 + i l2 5a/div 500s/div 8709 ta05c downloaded from: http:///
lt 8709 45 8709fa for more information www.linear.com/lt8709 typical application high power 300khz, negative boost converter generates a ?12v/4.5a output from a ?4.5v to ?9v input efficiency and power loss vs load current (?v in = ?5v) transient response with 2a to 4a to 2a output load step (?v in = ?5v) imon ss Cv in csp tg csn bg lt8709 8709 ta06a intv cc modepg rt sync gnd en/fbin fby bias intv ee intv cc v c isn isp v out C12v4.5a Cv in C4.5v to C9v Cv in l1 2.2h mp mn c in1 330f 2.2f c out1 100f2 10k 2.2f c in2 100f2 118k 100k 2m 13.3k r sense1 ? l2 2.2h ? 130 k 37.4 k r sense2 7m c out2 330f + 68nf 470nf 2.2nf 100pf + 2.2f c1 22f Cv in 0.47f 499 d1 l1, l2: wrth-cfwi, 2.2h, 74485540220 mn: infineon, bsc0901nsi mp: vishay, si7143dp r sense1 : 2m, 2512 r sense2 : 7m, 2512 d1: on-semi, mbrm110c in1 : oscon, 16v, 330f, 16seqp330m c in2 : 100f, 16v, x5r, 1210 c1: 25v, 22f, x7r, 1812 c out1 : 100f, 16v, x5r, 1210 c out2 : oscon, 16v, 330f, 16seqp330m load current (a) 0 efficiency (%) power loss (w) 100 80 9060 40 30 7050 75 3 64 2 1 0 1 1.5 2 8709 ta06b 3 3.5 4 2.5 4.5 0.5 i load 2a/div v out 200mv/div ac-coupled i l1 + i l2 5a/div 200s/div 8709 ta06c downloaded from: http:///
lt 8709 46 8709fa for more information www.linear.com/lt8709 fe20 (cb) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 detail a detail a is the part of the lead frame feature for reference only no measurement purpose 1112 14 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation cb detail a 0.60 (.024) ref 0.28 (.011) ref package description please refer to http:// www .linear.com/product/lt8709#packaging for the most recent package drawings. downloaded from: http:///
lt 8709 47 8709fa for more information www.linear.com/lt8709 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 03/16 corrected figure 6 corrected figure 9modified figure 15 modified schematic 1821 27 42 downloaded from: http:///
lt 8709 48 8709fa for more information www.linear.com/lt8709 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8709 ? linear technology corporation 2015 lt 0316 rev a ? printed in usa related parts typical application part number description comments lt3757a boost, flyback, sepic and inverting controller 2.9v v in 40v, 100khz to 1mhz programmable operating frequency, 3mm 3mm dfn-10 and msop-10e packages lt3758a boost, flyback, sepic and inverting controller 5.5v v in 100v, 100khz to 1mhz programmable operating frequency, 3mm 3mm dfn-10 and msop-10e packages lt3759 boost, sepic and inverting controller 1.6v v in 42v, 100khz to 1mhz programmable operating frequency, msop-12e package lt3957a boost, flyback, sepic and inverting converter with 5a, 40v switch 3v v in 40v, 100khz to 1mhz programmable operating frequency, 5mm 6mm qfn package lt3958 boost, flyback, sepic and inverting converter with 3.3a, 84v switch 5v v in 80v, 100khz to 1mhz programmable operating frequency, 5mm 6mm qfn package lt3959 boost, sepic and inverting converter with 6a, 40v switch 1.6v v in 40v, 100khz to 1mhz programmable operating frequency, 5mm 6mm qfn package lt8710 synchronous sepic/inverting/boost controller with output current control 4.5v v in 80v, rail to rail output current monitor and control, c/10 or power good 250khz, wide input range, buck-boost converter generates a ?5v output with up to 7a output current efficiency and power loss vs load current transient response with 2.5a to 6.5a to 2.5a output load step (?v in = ?12v) load current (a) 0 efficiency (%) power loss (w) 100 80 9060 40 30 7050 75 3 64 2 1 0 2 3 8709 ta07b 5 6 4 7 1 Cv in = C5v Cv in = C12v Cv in = C12v Cv in = C5v imon ss Cv in csp tg csn bg lt8709 8709 ta07a intv cc modepg rt sync gnd en/fbin fby bias intv ee v c isp isn v out C5v7a Cv in C4.5v to C25v Cv in l1 3.5h mp 2 mn 330f 2.2f c out1 100f3 10k 2.2f c in 10f4 143k 100k 1.5m 13.3k r sense1 r sense2 5m ? l2 3.5h ? 45.3 k 11 k c out2 330f + 68nf 470nf 3.3nf 100pf + c1 10f 2 2.2f 2.2f l1, l2: wrth-cfwi, 3.5h, 74485540350 mp: fairchild fdd4141 mn: infineon, bsc026n04ls r sense1 : 1.5m, 2512 r sense2 : 5m, 2512 c in : 50v, 10f, x7r, 1210 c1: 50v, 10f, x7r, 1210 c out1 : 16v, 100f, x5r, 1210 c out2 : oscon, 16v, 330f, 16seqp330m i load 5a/div v out 200mv/div ac-coupled i l1 + i l2 5a/div 200s/div 8709 ta07c downloaded from: http:///

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